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Welcome to Wireless Chip Designer - the only newsletter that covers the challenges of integrating analog design, analog mixed signal and RF–Wireless functionality into silicon. Please see below for address-change or subscribe/unsubscribe instructions. This Month's Table of Contents:
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1. Viewpoint – ExclusiveTrends in Wireless Consumer Electronics Drive AMSby Mike Demler, HSIMplus Product Marketing Manager, Synopsys (www.synopsys.com)
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2. News3G Licenses Increase Demand for Wireless Test Equipment in ChinaAccording to Frost and Sullivan, considering the imminent 2008 Olympics in Beijing, issuing of 3G licenses to ensure high-speed mobile networks is probable this year. This is likely to drive demand in the wireless test and measurement equipment. In fact, a recent report on Chinese Wireless Test and Measurement Equipment Markets revealed that the Chinese market earned revenues of $197.7 million in 2005 and is likely to reach $606.2 million in 2012. The Chinese government is set to further the growth of 3G technology in China by fostering a robust domestic telecommunications industry which may lead to tremendous investment in the telecom market and benefit both 3G terminal equipment makers and IT vendors. |
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Gold Sponsor: Chip Estimate Corporation Search IP. Estimate your Chip. FREE! |
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3. NewsDonation Prompts IP Encryption Standardization EffortSynplicity has joined the VSI Alliance (VSIA), the leading IP standards body for the electronics industry, and is donating its Open IP Encryption Methodology to the organization. The agreement provides VSIA with a license to use and modify Synplicity's copyrighted Open IP Encryption specification for the purposes of creating an industry IP encryption standard which will ease development and integration costs for FPGA and SoC design throughout the design chain. Furthering adding weight to this announcement, VSIA has created the IP Encryption working group, a sub-group of the VSIA IP Protection Pillar. Companies who participate in the group will be able to help shape an end product that addresses the needs of their company, while contributing to the definition of an industry standard. |
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4. NewsIP Program Gains New MembersSix new companies have joined the growing list of Cadence OpenChoice IP Program members; a program which enables interoperability and facilitates collaboration with IP providers to build, validate, and deliver accurate models optimized for Cadence design and verification solutions. These companies include: ChipIdea, Fabbrix; GDA Technologies, Ingot Systems, Intelliprop, and IPextreme. Since the OpenChoice IP Program's inception in 2004, more than 35 quality IP providers have signed up to offer customers the latest technologies in both verification and design IP, optimized for Cadence flows. The addition of these new members expands the current portfolio with memory controllers, libraries and interface protocols including PCIExpress, USB, Flexray, and SATA. The result is a further optimized electronics design chain and acceleration of customer time to market. | |
5. NewsDevelopment Platform Eyes W-CDMA/WiMAX StandardsAXIS Network Technology and Xilinx have introduced CDRSX, a common digital radio system (CDRS) development platform that increases power amplifier (PA) efficiency and reduces capital and operating costs for W-CDMA and WiMAX base stations. The CDRSX development platform consists of the Xilinx W-CDMA and WiMAX digital front-end (DFE) reference designs and the flexible AXIS Virtex-based development board to provide a power efficient, quick time-to-market route from concept-to-production for wireless digital radio cards. The AXIS CDRSX Development Platform offers OEMs the flexibility to quickly adapt to changes in specification or air interfaces. It includes a specially designed board containing RF preamps, ADCs, DACs, a Xilinx Virtex-II Pro FPGA to provide interface support for CPRI, OBSAI and digital I/Q connectivity and Virtex-4 SX55 FPGA for implementing digital radio signal processing functions, and an operating system for control of the board via Ethernet connection. |
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BRONZE Sponsor: Real Intent Don't build your chip without verifying every key aspect. Those SDC False and Multicycle path statements could cause your design to fail. Only PureTime Timing Exception Verification from Real Intent will insure that both false and multicycle paths are correct. For more information: http://www.realintent.com/products.html |
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6. NewsPartnership Optimizes SoC Power And ArchitectureSequence Design and Synfora have jointly created an integrated flow that incorporates Sequence's PowerTheater RTL power-analysis tool with Synfora's PICO Express Application Engine Synthesis (AES). This combination provides the user with unequaled insight into performance, area, and power for advanced SoCs early in the design, when analysis and design tradeoffs can have maximum impact. PICO Express bridges the SoC design productivity gap by enabling the automatic generation of optimal architectures and synthesizable RTL from untimed C algorithms. Integrating this solution with Sequence's PowerTheater, allows users to generate multiple trial implementations and then run PowerTheater to estimate power at RTL and, later, at the gate level. Strengthening this joint collaboration, Synfora has recently joined the InSequence Technology Partner Program, promoting EDA interoperability and advanced design methodologies. 7. International NewsXilinx Accelerates Growth of Electronic Design Innovation in ChinaXilinx Chairman, President and CEO Wim Roelandts recently underscored the company's commitment to accelerate growth of electronic design innovation in China. Among the key areas of the company's expansion are a multi-million dollar technology fund, dedicated support facilities including an applications development lab, an expanded third-party ecosystem and significant investment in local universities. According to iSuppli, Xilinx is already the number one programmable logic device (PLD) supplier in China with 59 percent market segment share and selling more PLDs to Chinese-based manufacturers and electronics designers than all other PLD suppliers combined. With widespread adoption throughout the region, Xilinx plays a key role in supporting China's drive for local technological innovation. Asia Pacific revenues for the company now represent 25 percent of overall revenues, as reflected in its most recent Q2 FY07 financial results. 8. International NewsRF Design Software Donated to Peking UniversityApplied Wave Research and Shanghai Research Institute of Microelectronics (SHRIME), Peking University, China, have announced that AWR is donating its entire suite of radio-frequency (RF) design software in a collaborative effort to advance Peking University's high-frequency design curriculum. The donation is the first step in a long-term program that will establish a joint RF design and research laboratory at the university's research institute. The laboratory will spearhead high-frequency research projects in Shanghai and develop unified process design kits (PDKs) and value-added RF intellectual property (IP) for key foundry processes in China. 9. In–Depth Coverage LinksRecently, several sources reported the premature decline of the structured ASIC market, with the added prognosis that the technology will never recover. Structured ASICs are dead? Not in our view! To learn more, read: “Structured ASICs Are Alive and Well.” System-level verification solutions require power of emulation to address the opposing forces of increasing complexity and shrinking design schedules. To learn more, read: “Emulation Gets the Nod vs. FPGA Prototyping.” |
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10. New BooksESD: RF Technology and Circuits |
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11. Happenings – ConferencesWAMICON 2006: IEEE Wireless and Microwave Technology ConferenceDecember 4-5, 2006 Clearwater, FL http://wamicon.eng.usf.edu/ SEMICON Japan 2006 IEEE International Electron Devices Meeting VLSI Design Conference 2007 2007 IEEE Radio & Wireless Symposium 2007 International CES Real-Time & Embedded Computing Conference Electronic Design and Solution Fair 2007 with FPGA/PLD Conference DesignCon 2007 International Symposium on Quality Electronic Design 2007 Embedded Systems Conference Silicon Valley Design Automation and Test in Europe (DATE) |
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WIRELESS CHIP DESIGNER e–NEWSLETTER CONTACTS
Editor: Cheryl Ajluni, cajluni@extensionmedia.com Editorial Director: John Blyler, jblyler@extensionmedia.com Advertising/Sponsorship Opportunities: Karen Popp, kpopp@extensionmedia.com Read past issues of Chip Designer, FPGA Developer and Wireless Chip Designer : www.chipdesignmag.com/enewsletters To subscribe, or change your profile, visit: To unsubscribe, email: Visit Chip Design:
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