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Welcome to Wireless Chip Designer the only newsletter that covers the challenges of integrating analog design, analog mixed signal and RF-Wireless functionality into silicon. Please see below for address-change or subscribe/unsubscribe instructions. This Month's Table of Contents:
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Cadence Technology on Tour 2006 The latest technology and flow demos at a location near you. |
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1. Viewpoint - ExclusiveEffects of EDA Evolution on RFIC Design
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The Cadence RF Design Methodology Kit - Intelligently manage parasitic extraction |
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2. NewsFPGA Market To Top $2.75 Billion By Decade's EndAccording to research conducted as part of In-Stat's Semiconductor Logic Markets
service, the Field-Programmable Gate Array (FPGA) market, with a quickly expanding array
of uses, is on a roll. It is predicting that the value of worldwide FPGA shipments will
increase from $1.9 billion in 2005 to $2.75 billion by 2010. Much of this revenue will
come from low volume shipments. The largest two end-use segments will be communications (both wired and wireless)
and industrial, whose combined market share of the FPGA market will increase from 73.8% in
2005, to 76.8% by 2010. |
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3. NewsIntegrated Modeling Environment Enhances A/MS Design ProductivityLynguent has announced its first product - the ModLyng Integrated Modeling Environment.
As a tool for analog/mixed-signal (AMS) IC design, it incorporates an easy-to-use
graphical user interface, is language- and platform-independent, and removes significant
barriers to the re-use of models. Consequently, it helps semiconductor and systems
companies save weeks in development time, which can improve a company's bottom-line by
hundreds of thousands of dollars per design project. Using Lynguent's new ModLyng
environment, engineers can create, maintain, debug, and translate their AMS models faster
than ever before. And, they can re-use the models in other designs, across a number of
target HDLs. Alternatively, engineers can create new models with ModLyng, which is
especially important in developing behavioral model blocks for speeding design simulation
and validation. The models may be exported to the same language in which it was written or
automatically translated to another language. ModLyng also features unique analysis and
debug capabilities. |
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4. NewsCollaboration Addresses Millimeter-Wave Applications
United Monolithic Semiconductors (UMS) and Ansoft Corporation have announced the implementation of a GaAs IC design methodology for millimeter-wave frequencies that utilizes on-chip electromagnetic extraction and a new Ansoft Designer/Nexxim RF design kit for the PH15 PHEMT process. This millimeter-wave qualified kit implements rigorous device modeling and validation by the foundry and is combined with advanced frequency-domain simulation for highly nonlinear and highly integrated circuits as well as integrated electromagnetic simulation for on-chip extraction. The Ansoft Designer/Nexxim design kit supports electrical design and physical circuit layout, enabling reliable MMIC design at millimeter-wave frequencies. The kit provides all parameterized electrical models and layout cells for hot and cold FETs, diodes, MIM capacitors, spiral inductors, thin-film resistors and distributed interconnects, such as transmission lines. The library will be available to Ansoft customers directly from UMS (www.ums-gaas.com) and is easily configured for use within the Ansoft Designer design management front-end, planar EM simulator and Nexxim circuit simulator. |
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5. NewsVerification Platform Ensures Analog Sign-OffA new version of the Opal test bench platform from Knowlent Corporation, Version 4.0,
enables the validation of high-speed interfaces used in SoC designs implemented in the
latest nanometer silicon technologies. Highlights of this new release include a new VIPer
test extension language, over 2X better performance of the binary test database, and
integration with the industry leading analog design environment. The Opal platform ensures
100% compliance of chip interfaces to their electrical specifications delivering analog
signoff for that portion of an SoC design. The increased flexibility, performance and
accuracy of this new release enables customers to better achieve analog signoff and
first-time product success. Knowlent is also announcing the availability of electrical
verification IP (EVP) for the PCI Express Gen 2 interface standard. This new EVP enables
testing of PCIe Gen2 interfaces when using the Knowlent Opal verification platform. | |
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6. NewsMMIC PDK Now Available For The Microwave Office Design SuiteApplied Wave Research now offers a process design kit (PDK) that supports Cree's
high-power silicon carbide (SiC) process. The kit enables monolithic microwave integrated
circuit (MMIC) designers to use Cree's MMIC process within AWR's Microwave Office software
environment. Designers can now improve productivity by applying AWR's industry-leading,
open, and integrated design platform to Cree's wide bandgap SiC MMIC foundry services and
discrete products. |
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Intel is hiring! Take a look here for more details....http://www.chipdesignmag.com/career.php |
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7. International NewsFujitsu and Lattice To Market Lattice FPGA/PLD Products In JapanFujitsu Limited and Lattice Semiconductor Corporation have signed a distribution
agreement in which Fujitsu Devices Inc. will be added as an authorized distributor of
Lattice's FPGA/PLD products in Japan. Fujitsu has been manufacturing Lattice FPGA products
under contract since March 2004. Under the new distribution agreement, Fujitsu and Lattice
will further strengthen their partnership to include both manufacturing and sales. The
agreement encompasses all Lattice products, including FPGAs manufactured using 90nm CMOS
technology at the 300mm wafer line at Fujitsu's Mie fab, as well as all other existing
products. In addition to incorporating these Lattice products into Fujitsu products,
Fujitsu will also promote the sale of Lattice products to specific customers through
Fujitsu Devices Incorporated. 8. International NewsTechnology Supports VHDL And Mixed Verilog/VHDL LanguagesThe VTOC core modeling technology from UK-based Tenison Design Automation now supports
the VHDL and mixed Verilog/VHDL languages. VTOC gives design teams comprehensive coverage,
speed, and accuracy for easily moving designs from RTL into high speed models for system
level design. The extension to support designs in VHDL and mixed Verilog/ VHDL means that
regardless of the original HDL, designs can be easily converted to high-performance models
which can be integrated at the cycle callable or bus transactional levels. Designers not
only gain an automated path to higher levels of abstraction and faster models in C++ and
SytemC, they also gain a homogenized design in a common language for simpler debugging and
ease of interfacing, as well as reuse with software and new system level designs. 9. In-Depth Coverage LinksAs market forces continue to push more analog and RF functionality into digital SoCs,
designers face a host of development issues. To learn more, read: "Analog-RF IP
Integration Challenges SoC Designers."
Chip Design Editorial Feature » If complexity and gate count are approximately correlated, then IP is becoming about 5
times more complex every 3 years. To learn more, read: "The Changing Face Of Re-Usable
IP."
iDesign Editorial Feature » |
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10. New BooksSynthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems In Synthesis of Arithmetic Circuits: FPGA, ASIC and Embedded Systems, the authors take
a novel approach of presenting methods and examples for the synthesis of arithmetic
circuits that better reflects the needs of today's computer system designers and
engineers. Unlike other publications that limit discussion to arithmetic units for
general-purpose computers, this text features a practical focus on embedded systems. Rapid System Prototyping With FPGAs The push to move products to market as quickly and cheaply as possible is fiercer than
ever, and accordingly, engineers are always looking for new ways to provide their
companies with the edge over the competition. Field-Programmable Gate Arrays (FPGAs),
which are faster, denser, and more cost-effective than traditional programmable logic
devices (PLDs), are quickly becoming one of the most widespread tools that embedded
engineers can utilize in order to gain that needed edge. FPGAs are especially popular for
prototyping designs, due to their superior speed and efficiency. This book hones in on
that rapid prototyping aspect of FPGA use, showing designers exactly how they can cut time
off production cycles and save their companies money drained by costly mistakes, via
prototyping designs with FPGAs first. |
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11. Happenings - ConferencesSemicon West Design Automation Conference HOT Chips 18 ARM Developers' Conference GSPx Conference and Expo Electronica |
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WIRELESS CHIP DESIGNER e-NEWSLETTER CONTACTS
Editor: Cheryl Ajluni, cajluni@extensionmedia.com Editorial Director: John Blyler, jblyler@extensionmedia.com Advertising/Sponsorship Opportunities: Karen Popp, kpopp@extensionmedia.com Read past issues of Chip Designer, FPGA Developer and Wireless Chip Designer : www.chipdesignmag.com/enewsletters To subscribe, or change your profile, visit: To unsubscribe, email: Visit Chip Design:
Copyright © 2006 Extension Media, Inc. All rights reserved. |