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This Month's Table of Contents:

1. Escape From Analog Alcatraz
2. Processor Integration To Bring IC Industry Consolidation
3. TSMC-Qualified 0.13 micron Process Design Kit Released
4. Synopsys Primerail Speeds Tapeout Of Mobile Phone IC Design
5. Library Speeds Wireless Communications Product Development
6. Embedded Intelligence Expects To Revolutionize The Mobile Industry
7. A/MS CMOS Process And Design Kit Now Available In Malaysia
8. Chartered Invests In Taiwanese Design Services
9. In-Depth Coverage Links
• Advanced Verification Drives Home Advanced FPGAs
• Transaction-Level Modeling Gains Further Momentum
10. New Books
11. Happenings – Conferences

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   >> Gold Sponsor: Chip Estimate
   >> Silver Sponsor: EVE
   >> Bronze Sponsor: Real Intent

1. Viewpoint – Exclusive

Escape From Analog Alcatraz

By Clive (Max) Maxfield

In my last Chips and Dips Column - Prisoner PCell Block A I waffled on about (a) the wonders of PCells that make folks giggle and grin and (b) the "gotcha" about PCells that makes users gnash their teeth and rend their garb.

Now, if you're a digital designer like yours truly, you may not have been exposed to these little PCell rapscallions, but the whole concept is actually rather interesting. Let's briefly recap the position to make sure we're all tap-dancing to the same beat (my dear old dad used to be a tap-dancer on the variety hall stage, so I know whereof I speak).

PCells (The Way Things Were)
Here's the deal in a nutshell. Unlike the vast majority of digital IC designers who tend to use only the standard logic cells that are placed before them, analog IC designers tend to enjoy "tweaking" and fine-tuning things. You should hear them having a good time at a party: "Maybe things will work better if this transistor channel is made a hair wider while that one is made a tad shorter," one will suggest in an excited whisper, and the melee will begin.

In "Ye Olden Days" when I was a lad, any such changes were implemented by the designers drawing the polygons (geometric shapes) that would form the various layers used to create the transistor in silicon. Initially, these polygons were drawn by hand. Later, Electronic Design Automation (EDA) tools came along that allowed the polygons to be "drawn" directly on the computer screen [we used the term Computer Aided Design (CAD) when referring to this class of tool in those days or yore]. The great thing about using the computer in this way was that you could easily resize and reshape the polygons and "push" (move) them around the screen; hence, this activity was often referred to as "polygon pushing".
Full Story >>

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2. News

Processor Integration To Bring IC Industry Consolidation

Functional integration in the portable media player and multimedia processor SoC markets will fundamentally change the value proposition for today's IC vendors. According to Gartner, Multimedia processor and portable audio/media processor integration has evolved from highly differentiated performance-based solutions to commodity ASSPs with massive average selling price (ASP) erosion. Integration of features and functions will lead to competition for fewer, more-integrated IC sockets. For example, with the advent of digital video recorder (DVR) and set-top box solutions, the industry has already seen significant integration. These solutions once comprised unique and expensive sets of chips, but integration has transformed them into commodity SoC devices that primarily compete on price. The release of HD-DVD and Blu-ray Disk formats will allow for massive integration of all these features into one single SoC device.

Functional integration will continue to provide clear benefits to the consumer - more features, better performance, lower costs and lower power use. However, this move toward integration is also creating significant challenges for IC vendors, which are competing for fewer, more-integrated ASSP sockets.

Gartner >> http://www.gartner.com

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3. News

TSMC-Qualified 0.13 micron Process Design Kit Released

In a joint effort with Mentor Graphics, Taiwan Semiconductor Manufacturing Company (TSMC) is releasing foundry-qualified process design kits (Mentor-PDKs) that support Mentor's entire custom/mixed-signal IC design flow. TSMC has long provided foundry- qualified design rule check (DRC), layout versus schematic (LVS), and parasitic extraction rule decks qualified for the Mentor Graphics Calibre platform, as well as Spice models for Mentor's Eldo Spice simulator. Starting with this latest release of the 0.13 micron mixed-mode and RF Mentor-PDK for TSMC's CM013RG process, TSMC now supports the entire Mentor Graphics ICstudio custom/mixed-signal IC design flow. This kit includes symbol library for Design Architect-IC schematic capture and parameterized layout generators for IC Station layout editor. The complete Mentor-PDK has been pre- qualified with the TSMC process. Design kits for the 90 nm and 65 nm nodes are currently being developed.

Mentor Graphics >> http://www.mentor.com
TSMC >> http://www.tsmc.com

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4. News

Synopsys Primerail Speeds Tapeout Of Mobile Phone IC Design

Cypress Semiconductor Corp. has successfully taped out its West Bridge Antioch peripheral controller multimedia 3G/3.5G mobile phone IC. It was designed using the Synopsys Galaxy design platform RTL-to-GDSII low-power solution, including the PrimeRail dynamic power network analysis solution. The multi-threshold CMOS (MTCMOS) power gating feature in the Galaxy design platform enabled Cypress to complete its ultra-low-power design with world-class performance and optimized standby current. PrimeRail, a key component of the Galaxy design platform, enables peak current analysis for the multiple power domains of the Power Gating-based design during physical implementation.

Cypress Semiconductor >> http://www.cypress.com
Synopsys >> http://www.synopsys.com

5. News

Library Speeds Wireless Communications Product Development

The WiMedia Wireless Library for use with Agilent Technologies' Advanced Design System (ADS) EDA software is now available. The new library helps wireless systems designers and verification engineers speed development of short-range wireless communications products such as Wireless USB. Supporting the WiMedia Alliance Physical Layer Specification Release 1.1, it provides preconfigured simulation setups, signal sources and fully coded BER analysis for simulation of the circuitry used in WiMedia designs. Agilent's WiMedia library works within the ADS environment and with the Agilent Ptolemy simulator to streamline design and verification of UWB orthogonal frequency division multiple-access (OFDM) based designs. The WiMedia Wireless Library also can be imported into Agilent RF Design Environment (RFDE), allowing RFIC designers to access WiMedia test benches within the Cadence design environment through links developed as part of the ongoing alliance between Agilent and Cadence Design Systems.

Agilent Technologies >> http://www.agilent.com

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6. News

Embedded Intelligence Expects To Revolutionize The Mobile Industry

Freescale Semiconductor has developed a programming method that significantly reduces time to first call when developing new phones. Based on direct customer feedback, the time to first call is reduced as much as 66%. Freescale's new method uses single- command programming which reduces calibration steps and practically guarantees system compliance. While the company's RFX275-20 RF subsystem is the first chipset to use this programming technique, newer generations (sampling soon) are being engineered to go even further in simplifying the layer-one programming. With Freescale's new embedded intelligence, the engineer simply enters a single command stating the desired channel and power level. This command sets the parameters and times the events such that system compliance is virtually assured.

Freescale Semiconductor >> http://www.freescale.com

7. International News

A/MS CMOS Process And Design Kit Now Available In Malaysia

X-FAB Silicon Foundries has announced that a modular 0.18- um analog/mixed-signal CMOS process and design kit is now available from its subsidiary in Kuching, Sarawak, Malaysia. The XC018 Master Kit, which supports state-of-the-art design flows, provides engineers designing CMOS low-power applications with a smooth and efficient path from design through physical implementation. The 0.18-um CMOS (XC018) technology is targeted for mainstream and advanced A/MS applications. It features 3-6 metal layers and supports applications at 1.8V, and 3.3V or 5V, noise reduced applications enabled by ISOMOS, and HV (32V) applications – specifically, power management, consumer electronics and industrial applications. The comprehensive XC018 Master Kit includes the Process Design Kit (PDK) as well as a low-power digital core library and I/O libraries for core and pad limited designs.

X-FAB Silicon Foundries >> http://www.xfab.com

8. International News

Chartered Invests In Taiwanese Design Services

Chartered Semiconductor Manufacturing has made a strategic investment in Gateway Silicon Inc. (GSI), a Taiwan-based firm specializing in ASIC/SoC design services and intellectual property (IP) development and integration. GSI is a spin-off of Taiwanese integrated device manufacturer Macronix International Company. The two companies will collaborate on developing and optimizing design services while extending GSI's expertise to leverage Chartered's portfolio of value-added solutions (VAS). The VAS offering consists of plug-in modules based on Chartered's proven CMOS process technologies, on its cost-effective wafer fabrication production capacity. They provide customers with efficient and reliable solutions for quickly developing differentiated products in markets such as wireless, consumer and security/industrial.

Chartered Semiconductor Manufacturing >> http://www.charteredsemi.com

9. In-Depth Coverage Links

Remember when you could work on your car? That was before it took sophisticated diagnostic tools and computer chips to change the oil. The expansion of FPGA capabilities has assured that the design and verification of FPGAs will follow the same path toward complexity. And it's about to get worse. To learn more, read: "Advanced Verification Drives Home Advanced FPGAs."
Chip Design Editorial Feature >>
http://www.chipdesignmag.com/display.php?articleId=720

TLM is one of the catalysts driving the acceleration of electronic system level (ESL) design methodology, as designers are using TL models for system modeling, verification, and most recently system and hardware design and implementation. To learn more, read: "Transaction-Level Modeling Gains Further Momentum."
iDesign Editorial Feature >>
http://www.chipdesignmag.com/display.php?articleId=813

10. New Books

Wireless Networking Technology
By Steve Rackley
ISBN-13: 978-0-7506-6788-3
ISBN-10: 0-7506-6788-5
Publisher: Elsevier

Today's wireless communications engineer needs to understand both wireless networking technologies and RF principles to maximize the performance of the wireless networks that they implement. Wireless Networking Technology: From Principles to Successful Implementation provides an "all in one" guide to wireless networking technologies and RF propagation methods, enabling the engineer to effectively solve implementation issues such as the impact of RF signal propagation on operating range, the degradation of range of input due to interference, the achievement of expected data throughput and the inter – operability of different equipment. This practical guide contains 'how to' implementation information, including quick checklists on installing, using and troubleshooting wireless networks, ranging from selecting the right wireless network technology for the application, ensuring good signal coverage and implementing best practice wireless security, to extending existing wired networks using wireless technology.

Elsevier >> http://www.elsevier.com

11. Happenings – Conferences

VLSI Design Conference 2007
January 6-10, 2007
Bangalore, India
http://www.vlsiconference.com

2007 International CES
January 8-11, 2007
Las Vegas, NV
www.cesweb.org

Real-Time & Embedded Computing Conference
January 25, 2007
Santa Clara, CA
http://www.rtecc.com

Electronic Design and Solution Fair 2007 with FPGA/PLD Conference
January 25-26, 2007
Pacifico Yokohama, Kanagawa, Japan
www.edsfair.com

DesignCon 2007
January 29-February 1
Santa Clara, California
www.designcon.com

Taiwan + China Semiconductor Outlook 2007
February 7, 2007
Santa Clara, CA
http://www.taiwan-china-outlook.com

International Solid State Circuits Conference (ISSCC 2007)
February 11-15, 2007
San Francisco, CA
http://isscc.org/isscc

FPGA 2007
February 18-20, 2007
Monterey, CA
http://conferences.ece.ubc.ca/isfpga2006

DVCON 2007
February 21-23, 2007
San Jose, CA
http://www.dvcon.org

PCB Design Conference West
March 25-30, 2007
Santa Clara, CA
http://www.pcbwest.com/conf_prog/technical.html

International Symposium on Quality Electronic Design
ISQED '07
March 26-28, 2007
San Jose, CA
http://www.isqed.org

The International Wireless Communications Expo (IWCE) 2007
March 28-30, 2007
Las Vegas, NV
http://www.iwceexpo.com

2007 Embedded Systems Conference Silicon Valley
April 1-5, 2007
San Jose, CA
http://www.embedded.com

Design Automation and Test in Europe (DATE)
April 16-20, 2007
Acropolis, Nice, France
www.date-conference.com

WIRELESS CHIP DESIGNER e-NEWSLETTER CONTACTS

Editor: Cheryl Ajluni, cajluni@extensionmedia.com

Editorial Director: John Blyler, jblyler@extensionmedia.com

Advertising/Sponsorship Opportunities: Karen Popp, kpopp@extensionmedia.com

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