Wizards of Electromagnetism

Due to the faster data transfer rate required in today’s consumer electronics market, interconnect design, such as Serial Advanced Technology Attachment (SATA) to PCB interface, can no longer be ignored. Designers must include electromagnetic effects (coupling, crosstalk, etc.) of SATA connectors with board traces for accurate signal integrity analysis. In this episode, a SATA connector is analyzed with FDTD EM simulation. Then the simulation file is exported as a design kit into a channel simulator so that the connector data can be re-used for signal integrity design along with other lumped circuit components.

Problem: How to bring a model of a SATA connection into a circuit simulator in order to optimize system perfromance around it?

Action: In the FDTD, we import the MCAD drawings, assign material properties, and define the mesh. Then we define the ports and excitation source and run the simulation. The multi-port frequency response is then exported as a DesignKit into the channel simulator where it can be combined with other lumped and distributed elements. The eye diagram and ultra-low BER contours are used as an optimization goal while tuning parameters such controlled impedance trace geometry, and equalizer settings.

Result: The impairments due to the connector can be optimally mitigated using the design variables available. Various connector types can be compared and the most cost effective one selected. Both tasks can be completed without expensive and time consuming cut-and-try spins.

Read the full details in our presentation EM Insights Series – Episode 7 – High Speed SATA Connector Modeling

See the full series at EM Insights Series

Accurate modeling and simulation of high speed digital connectors is critical for successful chip-to-chip and board-to-board interconnects. Using a 10.2 gigabit per second HDMI connector as an example, this episode demonstrates how a time-domain EM simulator helps in identifying problem areas in general and impedance discontinuities in an HDMI connector in particular. The speed of the simulator makes it easy to run multiple simulations for a better understanding and to optimize the impedance profile throughout the transitions. As a result, high performance connector designs can be achieved.

Problem: Minimize reflections due to the 29-pin HDMI connector used in a HDTV system.

Action: Simulate the step response of the connector in a 100-ohm test bench using a finite difference time domain EM simulator. Each simulation take only 20 minutes, allowing “what if” design space exploration. Time-domain reflectometry (TDR) display gives insight into the type (inductive versus capacitive) and physical location of the parasitic impedance changes for each configuration, making it easy to change the geometry for the next simulation run.

Result: Optimized impedance profile, close to 100-ohms differential throughout the connector path length.

Read the full details in our presentation EM Insights Series – Episode 6 – High Speed Digital Connector Optimization

See the full series at EM Insights Series

Posted by Colin

Two video interviews from DesignCon 2010

1. Dr. Eric Bogatin

Dr. Eric Bogatin interviewed me about our new Avatar-like ADS Momentum Stereoscopic Viewer with NVIDIA 3D Vision at our exhibit at DesignCon 2010. Click on the first image to play the video, hosted at the Real Time With DesignCon web site.

Here are some pictures the crew took of Marc and I hamming it up with a few colleagues and visitors:

2. Graham Bell

Graham Bell of EDA Café interviewed me about 3D EM, channel simulator, IBIS AMI, and our Agilent EEsof YouTube channel.

A Defective Ground Structure (DGS) is an intentionally designed defect on a ground plan, which creates additional effective inductance and capacitance.  This technique can be used to design microstrip lines with desired characteristics such as higher impedance, band rejection and slow-wave characteristics, while significantly reducing the footprint of the microstrip structure.  DGS structures are used in RF/microwave components (filters, dividers, amplifiers and high-speed digital designs.

However, designing DGS structures can be tricky.  Design tools typically don’t include closed-form DGS circuit models, so EM simulation is required to analyze and optimize these structures to meet the design goals.

Both time-domain and frequency-domain EM simulation can be used to simulate DGS structures.  Time-domain techniques, such as Finite Difference Time Domain (FDTD), can provide insightful TDR results.  Frequency-domain techniques, such as Finite Element Method (FEM), can very quickly find the resonant frequencies.  Both techniques provide very accurate results compared to measurements.

Read the full details in our presentation EM Insights Series – Episode 12 – Simulation of Defected Ground Structures

See the full series at EM Insights Series

My spoof video clip entered in this year’s DesignCon 2010 Video Contest is entitled Another Day In The Life Of an Agilent EEsof EDA Chiphead:

Every engineer wants an EDA tool that’s easy to use. But can things go too far? Find out in this (hopefully) hilarous 2010 sequel to my DesignCon Video Contest 2009 entry.

Please login to YouTube and give it a 5-star rating if you enjoy it!

On a slightly more serious note, here’s a brief video invitation by Eric Bogatin and his cat Maxwell to come to our Education Forum entitled “Practical Magic: Signal Integrity Problems Disappear with the Right Tools” that Eric (but sadly not Maxwell) will present at DesignCon 2010.

How to get tickets to see Eric? How about a DesignCon Exhibits PLUS registration ($100 value) free courtesy of Agilent Technologies? Copy our courtesy promotion code EXHAGI, surf over to http://www.designcon.com/2010/register/index.asp and paste EXHAGI into the promotion code box.

Exhibits PLUS badge gives you access to:

• Agilent Education Forum hosted by Dr. Eric Bogatin: Practical Magic: Signal Integrity Problems Disappear Using the Right Tools
• Keynote Addresses, Technical Panels, and Business Forum sessions
• Technology exhibition, including TecPreview presentations and exhibit floor receptions

Update 11/18/2009:We have Agilent co-authors contributing to six papers in the technical program. To see these you need a full program pass. You can get a discount off such passes at the same web page and using the EXHAGI promotion code.

• Introduction and Comparison of an Alternate Methodology for Measuring Loss Tangent of PCB Laminates
• Frequency Dependent Material Properties, So What?
• Rigorous Modeling of Transmit Jitter for Accurate and Efficient Statistical Eye Simulation
• Accuracy Improvements of PDN Impedance Measurements in the Low to Middle Frequency Range
• Evaluation of Relative Humidity and Temperature Effects of Scattering Parameters on Transmission Systems (0-26 GHz)
• Practical Study of Appropriate Measurement Bandwidth and Noise, Along with its Impact on Oscilloscope based Time and Frequency Measurements

Agilent is proud to be the official host sponsor of DesignCon.

A BGA package is very popular package style for high speed digital applications due to high density, low thermal resistance, and low inductance leads. However, a package is
the second most expensive part next to the silicon and can add 6 to 8 weeks to the cycle time. Given the very tight opportunity window for the majority of digital products, a failure to produce a successful package design can significantly reduce the profit margin or even kill the entire project.

Problem: Designers are challenged to get the desired BGA package performance right the first time.

Action: Method-of-moments EM simulation gives fast and accurate analysis of 45 mm BGA package designed in Cadence APD. Critical nets were imported into ADS using its Allegro Design Flow Integration capability.

Result: Simulated results showed candidate configuration would give acceptable s-parameter perfomance. Subsequent measurements confirmed the accuracy of this prediction and the acceptability of the solution.

Read the full details in our presentation EM Insights Series – Episode 5 – BGA Package Simulation

See the full series at EM Insights Series

The contactor is central to the design of high volume RF test fixtures. It acts as the final link connecting the RF test system to the RFIC package. Applications of contactors include high-volume test, characterization in the lab or burn-in test. In the past, high volume contactors were used primarily for testing digital ICs. However, with clock speeds exceeding 1GHz and higher operating frequencies of ICs, the performance degradation due to the contactors can be no longer ignored.

This episode demonstrates how FDTD EM simulations helps you to quickly analyze and understand the impact of the contactors to the overall test performance, consequently the production yield.

Problem: IC manufacturers find contactors from commercial vendors aren’t suitable because of the number of package sizes, styles and pad configurations in use. In-house design in required, but how to optimize the design without expensive and time-consuming cut-and-try experimentation?

Action: With FDTD simulation, the design of the contactor in its it’s usage context is quick and easy. It enables designers to quickly test and verify various different configurations and their effect. Impedance changes due to:

1. Contactor housing overlaying the PCB traces
2. PCB traces being wider than the contactor blades

…can quickly be assessed and mitigated.

Result: First pass success in designing and building a transparent test fixture .

Read the full details in our presentation EM Insights Series – Episode 4 – Contactor Design in High Volume RF Test Fixtures

See the full series at EM Insights Series

There are many EM simulation technologies and tools available in the market that antenna designers can use, but which is the best one for the job? This episode demonstrates the use of finite difference time domain (FDTD) simulation in the design of wireless network card antenna. The ultra-fast simulation capability of FDTD enables designers to quickly test and verify different configurations and sizes of antenna. A modern user interface enables designers to visualize the current and field pattern on the antenna surface and thus helps design smaller antennas.

Problem: Wireless network card antenna designers are oftentimes challenged to reduce the size but it’s a difficult design task without the aid of EM field solvers or visualizing current/field patterns on the antenna.

Action: With FDTD simulation, the design of a wireless network card antenna is quick and easy. It enables designers to quickly test and verify various different configurations and sizes of antenna. Modern visualization features enables designers to see the current and field pattern on the antenna surface, thus helping to design smaller antennas. In this example, the designers could quick try a “what if” experiment of adding a localizer hole. They also noticed a low current flow at the top, and experimented with size reduction in the areas of low current flow.

Result: Antenna design that is ~40% smaller in area, with no compromise in performance or cost.

Read the full details in our presentation EM Insights Series – Episode 3 – Wireless Network Card Antenna Design

See the full series at EM Insights Series

The major bottleneck in a planar microstrip patch antenna design is finding a field solver with sufficient capacity and speed to handle a large size array antenna. The situation becomes more complicated when the antenna is used for multiple bands. In the past, the antenna problem was usually broken down into small sizes that were integrated (linearly added) later without carrying out an EM simulation at the full structure level. Unfortunately, with this method, coupling at the large structure level is not taken into account. This episode demonstrates how improvements in method of moments field solvers aids designers of large array of microstrip patch antennas. 

Problem: Traditional method of moments field solvers require an amount of memory proportional to the square of the size of the structure being solved (as measured by numbers of nodes, N,  in the solution matrix). This is wasteful, because some nodes are weakly coupled and don’t require storage of their coupling matrix elements.

Action: Apply a modern method of moments solver that uses an amount of memory proportional to N log N.

Results: Structures such as 64-element antenna at C band, and a multi-band shared aperture C (32-element) and X band (128-element) array can be solved faster using the memory in a workstation PC. Larger structures that couldn’t be solved at all before now run within reasonable time and memory contraints.

Read the full details in our presentation EM Insights Series – Episode 2 – Planar Antenna Array

See the full series at EM Insights Series

IC design isn’t finished until it’s packaged. What is the upper frequency limit that the package can operate? Is it possible to use a lower cost package type to lower the final product cost? What about the performance of package isolation? As an example, LO to RF leakage performance of an up- or down-converter IC depends not only on the IC’s isolation performance but also on the package. In this episode, a 3mm×3mm, 16-pin Quad Flat No Leads (QFN) package is optimized to improve the frequency performance using EM simulation.

Problem: The desired −18dB return loss was achievable at 15 GHz but not for a new design at 20 GHz. Need to improve from −7 dB to −18dB without resorting to a more expensive package.

Action: Use EM simulation to performance several “what if” analyses. Experiment with increasing the width of input/output transmission lines (to adjust the impedance) and with doubling up the bond wires and lead frames (to minimize the transition to the wider line).

Results: 10 dB improvement in return loss. −18 dB spec met.

Read the full details in our presentation EM Insights Series – Episode 1 – QFN Package

See the full series at EM Insights Series