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Fahrvergnügen

bloggerCan ASIC verification be fun?

The German word Fahrvergnügen directly translated means “the joy of driving“, and anybody who has ever driven a...

Taken For Granted

bloggerEDA Blogger BoF meeting at ICCAD 2008: Wednesday 12 Nov, 1600-1800

After a first Birds of a Feather meeting at DAC 2008 on the whole area of EDA Blogging, there is another one at ICCAD...

Verification Vertigo

bloggerDynamic vs Formal papers - lets be fair!

I have just returned from the Haifa Verification Conference in Israel, and I have to say – what a wonderful little...

EDA Thoughts

bloggerCadence crash followed by an ambulance chaser

What a way to crash the former #1 EDA company: Start a hostile bid for another company amidst an uproar of...

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• Chip Design Trends

Chip Design Trends Research Services

Chip Design Trends BiAnnual Report "The Slowing of Moore's Law and its implications on the Chip Design market" - Now Available!

Key Findings Include:

  • Pre-Silicon design investigations grew by 18% compared to a year ago
  • New design activity surged in Europe, followed by increases in the Asia-Pacific region and relative flat growth in North America
  • Use of semiconductor IP continued to increase, with analog-mixed signal and digital-core IP showing the largest segment growth - up by 35%!
  • Hot markets include communications, data processing and industrial-medical.
  • Overwhelming evidence supports the slowing of Moore's Law:
    • Tracked complexity metrics (like die size, clock speed, process node etc.) are less than would be expected under Moore's Law
    • Semiconductor industry is functioning at eight active process nodes versus the historical four nodes.
    • The "Design Gap" of the '90's is now the "Manufacturing Gap" of the 00's - i.e., the productivity boost from EDA tools is less than would be expected.
    • Extremely high cost of capitalization of bleeding-edge fabs.

Basis of Report:

  • Over 44,000 unique worldwide and regional pre-silicon design investigations
  • Analysis and forecasting of key chip design metrics including power, die size, clock speed, analog vs. digital IP, metal layers, technology nodes, memory vs. age and much more

Available Now

Discount Price Available until April 30th: $1,950 (One Issue); $2,950 (Two Issues). Multiple copy discounts and site licenses available upon request.

Forecast the Future with Chip Design Trends Custom Research Reports

CDT Advantage:

  • A growing aggregated database of over 44,000 unique pre-silicon, chip architectural design investigations - precursors to chip starts - containing important complex SoC metrics such as power, die area, clock speed, IP, processor-memory-interface cores, technology nodes, metal layer, regional user-market breakdowns and more.
  • Access to the Chip Design property (print/online/e-Newsletters) readership, which represents leading Integrated device manufacturers (IDMs) - traditional chip design and manufacture vendor, fabless IP companies, EDA tool suppliers, semiconductor equipment vendors and foundries.
  • As appropriate, access to the Chip Design affiliate sponsor subscribers, including leading chip, EDA and semiconductor organizations
  • Chip Design's cadre of leading technology and business editors/analyst

For more information email Melissa Sterling or contact her at +1 415-970-1910.

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