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Top Stories from the E-Newsletters

• Configurable Power Management ASICs – Today’s System Glue IP Designer & Integrator, May 2008
• Configurable Power Management ASICs – Today’s System Glue Chip Designer, May 2008
• The Case for Heterogeneous Multi-Core SoCs IP Designer & Integrator, March 2008
• The Case for Heterogeneous Multi-Core SoCs Chip Designer, March 2008
• Editor's Note IP Designer & Integrator, April 2008

Top Commentary

• [Editor's Note] Synopsys and the Power of Programmability 5-27-2008
• Prototyping as Productive Verification Methodology 5-9-2008
• Editor's Note: EDA Industry Caught in the Middle 4-16-2008
• Wither ESL 2.0 -- Are you ready to bite the bullet? 4-4-2008
• What makes chips different? 3-14-2008

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Top Stories

• MIPS Partners with Microchip for PIC32 Design Challenge 7-1-2008
• New Release of Lattice FPGA Design Tools 5-5-2008
• New Release of Lattice FPGA Design Tools 5-5-2008
• Vimicro Picks MIPS for Analog/Mixed-signal IP 4-2-2008
• R&D Agreement Plots Sub-32nm Memory Process Generations 1-31-2008

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Chips - ASIC and ASSP Low Power IP Design, Verification, Integration DFM-DFY-Verification Electronic System Level (ESL) SOC Interfaces

Memory Programmable Logic Analog/Mixed Signal Chip-Package-Board Emerging Technologies

ZeBu™: A Unified Verification Approach for Hardware Designers and Embedded Software Developers

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• [Editor's Note] Synopsys and the Power of Programmability
• Prototyping as Productive Verification Methodology
• Editor's Note: EDA Industry Caught in the Middle
• Wither ESL 2.0 -- Are you ready to bite the bullet?

More commentary...