This week’s blog highlights collection is concerned with AI and connected vehicles, sometimes both. There are quests to explore myths, and searches for answers for power management and software security too.
News Stories Archive
There are traps and lures in the IoT, as discussed by ARM and Maxim Integrated; Xilinx believes a video tutorial is a good use of time; Get cosy with SNUG for some insight; and ON Semiconductor is keeping an eye on you
How AI can be used for medical breakthroughs; What’s wired and what’s not; A new compiler from ARM targets functional safety; Industry 4.0 update
This week’s collection of blogs is concerned with security and safety after Mobile World Congress and ahead of Embedded World. Following NXP and Cadence in Barcelona, ARM, Mentor Graphics and Synopsys, take on automotive design, with safety, audio and IP, respectively.
Among this week’s topics: two important announcements- the OpenFog Consortium and IEEE Standard for the Functional Verification Language e; a panel discusses the Internet and beyond; Mentor Graphics applies IoT to PCB design; FASTR accelerates the connected car and why USB is not as easy as 123
This week’s blogs show the human face of automated driving; and why energy should be taken seriously. There is lift-off for SpaceX to bring more satellite comms and a poetic turn, in the style of Rudyard Kipling’s classic poem.
What happens at CES doesn’t stay in Vegas for long – connected vehicles, homes and advanced graphics are all blog topics. In other news, we welcome a new blog business and compare EDA to sports giants.
Today’s the day -Bluetooth 5 and ARM is ready; A vision for disruptive technologies; When being better connected counts; Memory – the jewel in the crown; Functional Safety, in three video parts
his week, several blogs pose the question: How far does the IoT reach? Into space, the summit of Everest or just making industry smarter? Synopsys helps reduce layout time; Dassault Systemes prescribes Precision Medicine
New specs for PCI Express 4.0; Smart homes gateway webinar this week; sensors – kits and tools; the car’s the connected star; Intel unleashes AI
Videos/PodcastsLegacy vs New IP – Trends in IOT JPG and Drone Applications
Engineering vs. Science in Public Policy
Low Power Engineering
SEMI Pacific NW Breakfast Forum: The Future of Communication Attention â Semiconductor professionals in the Pacific Northwest! SEMI 2017 is having another...
How can the Chip Community Improve the Industry for IOT Designers? Meeting the 20 billion IOT devices prediction by 2020 will require the semiconductor industry...
- Renuka: So true for embedding sustainability aspects right from design mode.
- Dennis Brophy: I’m not certain I ever questioned an online offering for technical information coming out of...
- Jeff Brower: Chris- Your analysis is very good. I have been using your blog post since last year for reference in...
- Justin Nescott: It’s a honor to be included in your blog review. I’m glad you found the ANSYS Top 5...
- Daniel Payne: I think there’s a typo in the third paragraph with “0.07V”, should instead be 0.7V....
Jim Kobylecky Besides, eating a coding rivet from time to time has to be a whole lot less painful than the alternative. Hmm,...
Srini What a great prediction/foresight Gabe! We have indeed DVCon happening in India this year, 2014, intact little...
jblyler Hi Steve. Thx for the correction. I mentioned it to the editor and updated the post. Cheers. -- John
Windy Windy... DAC 2013 Pictures | JB's Circuit...
An interconnect, also referred to as a bus matrix or fabric, serves as the communication hub of multiple intellectual property (IP) cores inside a system on chip (SoC). As the capacity of today’s SoCs continues to increase dramatically…
Finding the optimal configuration options that meet the requirements of a particular system requires complementary design tools to enable the designer to rapidly explore and correlate trade-offs in performance, power, and area (PPA).
The recent advent of low-cost cluster management offerings have allowed IT organizations to adopt failover techniques for a variety of mission-critical systems, including the ENOVIA Synchronicity DesignSync Design Data Management (DDM) product from Dassault Systèmes. This paper provides a detailed example developed with a current semiconductor customer.
When templates, methodologies and verification IP components were integrated, suddenly simulation speed took a nosedive. Here’s why.
A new method for dramatically reducing CPU and RAM resource requirements.
New techniques that are making advanced SoC verification possible.
The relative advantages and disadvantages of single-threaded tag and multi-threaded non-blocking protocols.
A trove of technical videos and presentations from Cadence and other companies.
RTL flows are straining to meet the demands of most product teams. Moving up a level of abstraction is no longer an option.
A new design methodology is needed for rapid layout prototyping, in-design signoff and to improve collaboration between schematic and layout designers.