• EdXact: Bringing Innovation Into The Verification Flow
  


• InCyte
  Chip Estimate Corporation


• Semiconductor Technologies > IP--Core - PLL and DLL Hard Macros
  True Circuits, Inc.


• Platform Express
  Mentor Graphics


• SafeNet Security IP
  SafeNet, Inc


• MOSAID Virtual Silicon Semiconductor IP
  MOSAID Virtual Silicon Semiconductor IP


• Carbon Design Systems' SOC-VSPT
  Carbon Design Systems


• True Circuits Product Showcase
  True Circuits, Inc.


• InCyte from Giga scale IC
  Giga scale Integration Corporation


• Accelerate Forward with Poseidon Systems
  Poseidon Design Systems


• PCI Express Integration and Verification
  Integre Technologies


• Celoxica
  Celoxica


• Programmable Digital Frequency Synthesizer (DFS) PLL
  Virtual Silicon


• TimingDesigner
  The Chronology Division of Forte Design Systems


• Synplicity
  Synplicity, Inc.


• NEW from Summit Design
  Summit Design


• Tuner & Builder
  Poseidon Design Systems


• Develop DFM Tools. Better. Faster.
  SoftJin


• cLGA® socket
  InterCon Systems


• On-Demand Web Seminar Sponsored by Avnet Electronics Marketing
  Avnet Electronics Marketing

EdXact: Bringing Innovation Into The Verification Flow

EdXact is an innovative EDA company dedicated to IC parasitic analysis and reduction. It has been created with the mission to help IC designers optimise post-layout simulation, maintain verification accuracy and meet time-to-market goals. With IC designs targeting nanometer processes, backend verification becomes a major bottleneck in the design cycle, which prevents designers to meet their time-to-market and time-to-volume targets. The overall goal of EdXact's technology is to help reducing the number of re-spins that are necessary today to produce complex ICs.

Efficient parasitic modelling is the key
EdXact's team has a strong background in physical verification, signal integrity analysis, substrate and interconnect analysis, delay and crosstalk modeling, as well as in parasitic extraction techniques. The company is headquartered in Grenoble, France, which reinforces its collaboration with R&D groups from Universities and Laboratories.

Today, EdXact is the leading provider of standalone Model-Order- Reduction technologies. It's mathematically proven algorithms are among the first in the market to be able to handle mutual inductors and cross-coupling capacitors without compromising the accuracy of the underlying model. The company's patent-pending techniques dramatically accelerate backannoted simulations in very large designs, while achieving sign-off accuracy.

Seamless integration into your design flow
EdXact is a niche player, aiming at boosting existing tools and flows by an order of magnitude and adding innovation for very special topics.

EdXact's tools are developed to integrate within your existing flows. Close cooperation allows the combined tools to be completely interoperable and user-friendly. The seamless integration with your EDA software provides an optimized and validated flow that is faster, much more efficient and still accurate in order to meet sign-off requirements. Boosting your existing tools EdXact sells to IC and SOC designers inside fabs, IP providers and design houses. EdXact's products have already been selected by companies based in Europe, in the USA and in Japan. They have been successfully used for circuits with integrated spiral inductors, analog-digital converters, VCOs, LDOs, power amplifiers, as well as with very dense memory ICs, imaging ICs, microprocessors and many others. Customers are impressed by the speed improvements that are achieved, and very pleased to be able to use their simulation tools for new designs that otherwise would have been much too large.

SOLUTIONS

Jivaro
Jivaro is a parasitic elements reduction platform that enables the speed up of physical design analysis tools by applying reduction techniques while keeping results accuracy. It is composed of a large set of classic or innovative patent pending model order reduction algorithms, and of a proprietary numerical data base allowing multi-threaded and distributed computations.

Based on this platform, EDXACT has developed 2 different reduction tools JivaroD and JivaroA , as well as an interconnections analysis tool Comanche. As major benefits, the reduction tools allow a number of simulation runs in the same time budget, with a preserved accuracy, thus improving the chances for a successful tape-out on time. The simulation time for larger designs turns from infinite into hours, see minutes, and disk and memory requirements for simulation tools decrease substantially.

Users can also apply different degrees of reduction on different parts of the design, from absolute accuracy preservation down to very aggressive reduction rate. They naturally integrate in between the parasitic extractors and the physical verification tools

JivaroD is a high volume parasitic networks reduction tool that performs the reduction of R, RC, RC lumped and RC coupled networks. It can handle parasitic files of many gigabytes. It supports the DSPF and SPEF formats.

JivaroA is an analog/mixed-signal extracted circuits reduction tool that performs the reduction of R, RC, RCC, RLC and RLCK circuits and can handle files of a few gigabytes. It supports the SPECTRE and HSPICE post extraction formats. It is integrated in the Cadence Virtuoso and analog Artist platforms.

Comanche

Comanche is an accurate interconnections analysis tool that can be used within the physical verification flow as a sanity check to detect "gross" violations before going into time consuming physical analyses.

Comanche features extremely fast resistance, S,Y,Z, parameters and Elmore delay calculation capabilities and can detect a bunch of problems such as opens and shortcuts, risk of IR drop, insufficient via insertion, unbalanced interconnections carrying differential signals, I/O inadequacies for RF circuits, and many others.

InCyte

InCyte Features
Chip Estimate's InCyte adds accuracy and what-if analysis to the complex process of early chip planning. InCyte is used for refining your chip specification, including exploring and quantifying IP and process technologies, performing what-if analysis to refine design specifications, and to achieve the optimal balance of functionality, performance and cost. Die size, power, leakage, yield and production chip cost are estimated, and package recommendations are offered. InCyte estimates are based on actual foundry, ASIC vendor and IP vendor technology data models, and accuracy is within 98% of silicon. InCyte provides accurate estimation of the following key metrics.

• Die area - Total die size and bounding, factoring in all specified IP and design components.
• Power - Dynamic power consumption computed based on individual design components, factoring in frequency, switching activities, gate and IP data.
• Leakage - Static power consumption computed and broken down by core, I/O, hierarchical block, as well as each IP macro.
• Yield - Based upon industry or user-defined logic and memory defect density data, cumulative chip yield is calculated.
• Cost - Production chip cost calculated utilizing industry wafer pricing, yield, test & assembly, package, and non-recurring engineering cost data.

InCyte's analysis of final production chip cost builds on the system's technical estimation results, factoring in economic data gathered from across the semiconductor design chain, to provide users with an accurate estimation of packaged chip cost. Including an extensive database of package options, InCyte recommends a package based upon technical estimation results, and then provides volume based package pricing. Industry silicon wafer pricing data and defect densities enable systematic yield analysis providing 'good die' cost. InCyte's analysis of design components provides an estimation of test & assembly costs while industry non-recurring engineering costing data provides process specific mask cost estimations. The result is a complete budgetary quote reporting all of the factors which comprise production chip cost.

Industry wafer pricing, defect data, and packaging data are automatically updated quarterly by the InCyte software, ensuring that estimations are always based on the latest available economic data. InCyte's economic models which drive the calculation engine are also user customizable. Users may override many aspects of the economic analysis to tailor estimations to their needs.

InCyte users have the option of performing a lifecycle analysis to forecast chip cost over time, taking into account decreasing wafer costs, improving defect densities and other parameters. Return on investment (ROI) analysis enables users to understand over what timeframe and volume non-recurring engineering costs may be amortized and profitability on a design may be achieved.

Using InCyte
Integrating InCyte into a chip planning process is easy, and the input required is minimal. Specifications of gate count, memory size, number of I/Os and IP blocks are used to generate an estimate that can be used to assess the technical and economic feasibility of a design. InCyte includes a comprehensive IP catalog from which users can select technology nodes, process variants and IP macros under consideration. Users can also import IP lists they generate while searching and selecting IP in the ChipEstimate.com IP catalog. InCyte utilizes technology models, provided by Chip Estimate, generated from the same design kit data used by chip implementation tools. This results in accurate, foundry, ASIC vendor, and IP library vendor specific estimations which correlate to within 98% of silicon. Users can perform rapid what-if analysis to compare their design across technology nodes, processes, IP options, and varying chip specifications.

Supported Foundries and IP Library Vendors
InCyte enables accurate chip estimations specific to processes and IP libraries from leading third party foundries and IP vendors. Please visit ChipEstimate.com for an extensive list of supported foundries and IP vendors. Additional foundries and IP library vendors may be added as well.

Output
Estimation results are output in various user selected formats including charts, reports, and tables describing die area usage, chip bounding, dynamic and static power consumptions, yield, and production chip cost. A preliminary chip floorplan is also generated. Budgetary quotations providing a comprehensive breakdown of production chip cost are also provided. Users may export all technical and economic estimation results in Microsoft Excel format. Design specification data may be exported in industry standard Verilog and LEF/DEF formats to link InCyte results directly to the chip implementation flow. InCyte outputs are compatible with EDA implementation tools from all major vendors. To get started with InCyte, click here to learn more about pricing and availability.

Chip Estimate Corporation
10050 N Wolfe
Road SW1-266
Cupertino, CA 95014
USA
Telephone: 408.255.0444 Telephone
Fax: 408.255.0344 Fax
sales@chipestimate.com
www.chipestimate.com

Semiconductor Technologies > IP--Core - PLL and DLL Hard Macros

PLL and DLL Hard Macros
True Circuits' complete family of standardized, silicon-proven, lowjitter PLL and DLL hard macros spans nearly all performance points and features typically requested by ASIC, FPGA and SoC designers. Using robust state-of-the-art circuits, a methodical and proven design strategy, and close associations with the world's leading fabs and IDMs, True Circuits is able to quickly and reliably create new and innovative designs in a variety of advanced process technologies. True Circuits' clock generator, spread spectrum, low bandwidth, high resolution and deskew PLLs support wide operating frequency ranges and multiplication factors over which they deliver optimal performance, eliminating the need for PLL generators that attempt to optimize performance at a single operating point. The clock generator PLL is available with multi-phase outputs and 4 bits of precise factional-N control. The high resolution PLL provides frequency modulation and very high frequency resolution with over 16 bits of control and very low long-term jitter. All PLLs are available in small sizes for easier integration.

True Circuits' DLLs delay a set of signals by precise and adjustable fractions of a reference clock cycle independent of voltage and temperature. These DLLs have flexible form factors for easier integration and are ideal for high-speed DDR and other interface applications.

True Circuits' high-quality, low-jitter, silicon-proven timing hard macros are available for immediate delivery in a range of frequencies, multiplication factors, sizes and functions in TSMC, UMC and CHRT processes from 0.18‘m to 65nm.

Features

• Clock Generator, Spread Spectrum, Low Bandwidth, High Resolution and Deskew PLLs
• DLLs for high-speed DDR and other interface applications
• Low-jitter and very process tolerant
• Versatile, with wide output frequency and multiplication ranges (1-4096)
• Small sizes and flexible form factors for easier integration

Deliverables

• Available in TSMC, UMC and CHRT processes from 0.18‘m to 65nm
• GDSII and LVS Spice netlists
• Behavioral, synthesis and LEF models
• Extensive user documentation
• Integration support to ensure successful tape outs

True Circuits, Inc.
4300 El Camino Real
Suite 200
Los Altos, CA 94022
USA
Telephone: 650.949.3400 Telephone
Fax: 650.949.3434 Fax
timing@truecircuits.com
www.truecircuits.com

Platform Express

Today's SoC designs require the integration of hundreds of sophisticated IP blocks from various sources. As a result, designers must invest everincreasing amounts of time and effort to understand the behavior of each individual IP block and its interaction with the surrounding circuitry. To speed up the design cycle, a platform-based methodology can be used. Platform-based design is an IP reuse strategy that facilitates the creation and verification of designs containing sophisticated IP from many different sources. Platform ExpressT, Mentor Graphics' platform-based design product, enables design creation and verification by automating IP reuse. The product documents all aspects of IP using the IP-XACTT XML databook format provided through The SPIRIT Consortium. The IP-XACT specification uses XML to create a machine-interpretable IP databook; it includes design information that software tools then use to automatically configure and integrate an IP block into a design. Mentor Graphics was the key developer of the core technology behind The SPIRIT Consortium's IP-XACT specification. Since donating that technology, Mentor has continued to advance the specification by developing design tools that bring the benefits of the specification to the end user. Using the tool and its large number of sophisticated generators, SoC designers can rapidly create and verify their system designs by automating complex, error-prone design creation, IP integration, power domain creation, software generation, verification steps, and a configurable build environment to enable easy design handoff. Based on standards throughout, Platform Express is supplied in Eclipse plug-in format, enabling the tool to operate as part of a larger, customized, design environment. Platform Express provides a new set of generators that support 0-Inr Checkerware verification IP, as well as PSL and OVL assertions. The product also features direct links to the Mentor Graphics QuestaT verification environment and provides a framework for enabling other verification formats.

The SPIRIT ConsortiumT is a global non-profit organization focused on establishing multi-faceted IP/tool integration standards that drive sustainable growth in electronic design. The Consortium currently provides technical specifications that are helping the industry integrate multi-vendor design-flows efficiently. These specifications will benefit integrated device manufacturers by providing faster time-to-market through automated IP configuration, integration and verification. The cooperative development environment of The SPIRIT Consortium has been extremely successful. The IP-XACT specification is the first of several specifications that will be sent to IEEE for consideration of official standardization. The current version of IP-XACT, which addresses an RT-level system integration and configuration specification, has been delivered into the P1685 IEEE standards process.

Mentor Graphics
8005 SW Boeckman Rd
Wilsonville, OR 97070
USA
Telephone: 800.685.7000 Toll Free
Fax: 800.547.4303 Fax
platformex_info@mentor.com
www.mentor.com

SafeNet Security IP

Silicon-proven Security Systems You Can Trust

SafeNet's IP security solutions deliver the advanced levels of security mandated by new industry standards and market requirements for improved protection of networking and communication systems. SafeXcel IP enables chip vendors to build feature-rich, complete security systems into next-generation SoCs. SafeNet not only provides the best security IP in the industry, we also provide a complete security software solution that is pre-integrated with hardware IP, thereby enabling you to deliver a complete hardware/software system to your customers.

SafeXcel IP - Inline Security Engine

The award-winning SafeXcel IP Inline Security Engine takes a significant step beyond traditional SoC security architectures by deploying micro-programmed hardware for full data plane packet classification, filtering, and flow processing for every packet. The result is superior data rates across all packet sizes and a significant reduction of general-purpose processor utilization for security functions. Its exceptional small packet performance make the security engine an ideal solution for securing Internet applications such as VOIP.

Why Select Security IP from SafeNet?

• Silicon-proven and reliable IP
• Robust high-speed implementations of complete security processing systems and individual algorithms
• Fast and easy to integrate
• Significant value-add through security software for complete HW/SW system for customers
• Flexible layered design
• Complete range of configurations to meet specific design goals
• World-class technical support

Award-winning Security Solution

SafeNet's SafeXcel IP Inline Security Engine was recognized by Frost and Sullivan as a unique silicon-proven security solution that enables robust Gigabit-level security processing for next-generation SoCs while reducing design cost and time to market.

"This award also recognizes SafeNet's unique approach in bringing to market not only robust hardware security components, but integrated hardware and software solutions that add significant value to OEM customers."
--Frost & Sullivan

Inline Security Engine -- Features

Support for IPv4 and IPv6, jumbo packets, IPSec and SRTP packet transforms, NAT, NAPT, NAT-T, extended sequence numbers, IP option and extension header muting, complete IP header modifications and updates (length, next-header, TTL, and checksum). Crypto support: DES/3DES (ECB, CBC), AES-128/192/256 (ECB, CBC, CTR), SHA-1 / HMAC, SHA-256 / HMAC, MD5 / HMAC, GHASH / AES-Galois Counter Mode, AES-XCBC-MAC-96, Pseudo RNG for IV generation.

More information

Watch our on-demand Webinar or download the white paper "Security in Silicon"
www.safenet-inc.com/ChipDesign

For more information about SafeNet's award-winning security IP portfolio, please call 443-327-1442 or contact us at OEMNetworking@safenet-inc.com

SafeNet, Inc
Telephone: (443) 327-1442
OEMNetworking@safenet-inc.com
www.safenet-inc.com

MOSAID Virtual Silicon Semiconductor IP

MOSAID Virtual Silicon develops and markets a broad line of process specific, semiconductor intellectual property (SIP) products for the world's leading foundries in 180nm, 130nm, 90nm and 65nm process technologies.

Key products include:

MOSAID Mobilize^TM -- Award winning, complete power management platform for 130nm and 90nm SoC designs that can drastically reduce static leakage and dynamic power without requiring special implants or triple well. Key components of the MOSAID Mobilize platform include:

• 100X reduction in static leakage with Patented Gate Bias Technology
• Up to 80% lower dynamic power
• Low leakage on "G" process
• MOSAID Mobilize components include: Power Island Manager, Standard Cells, Programmable I/O, MOSAID Maestro PLLs
• NEW: MOSAID Mobilize 90nm Single-port SRAM Compiler! Generates the industry's lowest power and lowest leakage SRAM memories.

MOSAID Maestro^TM -- A fully integrated, programmable Delta-Sigma Fractional-N PLL digital frequency synthesizer targeted for consumer and high-speed networking applications.

MOSAID Maestro PLL products are available for various 65nm, 90nm and 130nm processes and deliver a range of features including:

• Ability to synthesize clock up to 3.0GHz
• Input range 1.0MHz - 300MHz
• Output range 36.9kHz - 3000MHz
• 26 bit Frequency Multiplication factor 0.50000 to 999.999878
• Spread spectrum & Deskew
• Glitchless frequency changes
• Low cycle-to-cycle jitter of +/- 15ps peak to peak max @400MHz
• Low power; 1.4mW@1.2V/400MHz
• Small Area 0.04mm2 enables placement in the I/O ring or the core
• Test chip validated

MOSAID Memorize^TM -- A complete DDR and DDR2 SDRAM memory controller plus interface provided as a blend of hard and soft IP delivering maximum flexibility and high data rates.

MOSAID Memorize is comprised of the following components:

• Complete DDR/DDR2 SDRAM Controller logic delivered as RTL-based IP for the best fit into customers tool flow and design methodologies
• Incorporates advanced command re-ordering and scheduling and automatic precharge and activate scheduling to maximize bus utilization
• MOSAID's unique Interface Timing Module (ITM) library composed of critical Controller logic close to the I/Os delivered as hard IP blocks for greatest system performance
• Master and Slave DLL library delivered as hard IP for centering strobes in data eyes and the timing of DDR data edges for write operations
• Application specific SSTL I/O library including all required buffers, filler, power, and ground cells.

In addition to these SIP product lines, MOSAID Virtual Silicon also offers standard cell libraries, application specific and programmable I/O libraries and compilable memory components.

All of our products are designed to satisfy the demanding requirements of designers who need the highest quality and maximum performance for their SoC designs. IP products labeled as Silicon Readyr have been verified in silicon.

Visit us on the web at www.mosaid.com and register in our Customer Center for access to complete technical datasheets and product downloads.

MOSAID Virtual Silicon Semiconductor IP
3255 Scott Blvd, Ste.1-104
Santa Clara, CA
Telephone: USA
sip@mosaid.com
www.mosaid.com

Carbon Design Systems' SOC-VSPT

SoC Development Platform

With Carbon's RTL compiler and wizard technology, RTL can be automatically imported as a high-performance compiled object into any SystemC simulator, including ARM's RealViewr SoC Designer. For the first time, there is a design flow that provides accurate hardware profiling, integrated hardware and software debug, and execution of software on a hardware model months before silicon exists.

SOC-VSP enables system architects to get an early start on architectural analysis by leveraging legacy RTL to rapidly create a fast system model. SOC-VSP adds cycle-accurate hardware profiling to uncover any architectural deficiencies early in the design cycle. Software developers get an early start validating and debugging their firmware on a hardware-accurate model. SOC-VSP's integrated hardware debug features allow side-by-side hardware and software debugging in the RealView environment. Carbon's optional library of bus protocol transactors enables Carbonized RTL models to plug into a system-level model with a transaction-level interface.

SOC-VSP provides a high-performance, hardware-accurate chip model that can be rapidly assembled and used to validate a chip's architecture, firmware, and hardware on an engineer's desktop.

Carbon Design Systems
Telephone: +1.781.890.1500
Fax: +1.781.890.1711
info@CarbonDesignSystems.com
www.CarbonDesignSystems.com

True Circuits Product Showcase

PLL and DLL Hard Macros

True Circuits’ complete family of standardized, silicon-proven, low-jitter PLL and DLL hard macros spans nearly all performance points and features typically requested by ASIC, FPGa and SoC designers. using robust state-of-the-art circuits, a methodical and proven design strategy, and a close association with the world’s leading silicon fabrication vendors, true Circuits is able to quickly and reliably create new and innovative designs in a variety of advanced process technologies.

True Circuits’ clock generator, spread spectrum, low bandwidth, high resolution and deskew PLLs support wide operating frequency ranges and multiplication factors over which they deliver optimal performance, eliminating the need for PLL generators that attempt to optimize performance at a single operating point. the clock generator PLL is available with multi-phase outputs and 4 bits of precise factional-N control. the high resolution PLL provides frequency modulation and very high frequency resolution with over 16 bits of control and very low long-term jitter. all PLLs are available in small sizes for easier integration.

True Circuits’ DLLs delay a set of signals by precise and adjustable fractions of a reference clock cycle independent of voltage and temperature. these DLLs have flexible form factors for easier integration and are ideal for high-speed DDr and other interface applications.

True Circuits’ high-quality, low-jitter, silicon-proven timing hard macros are available for immediate delivery in a range of frequencies, multiplication factors, sizes and functions in TSMC, UMC and Chartered processes from 0.25µm to 65nm.

Features

• Clock Generator, spread spectrum, Low Bandwidth, high resolution and Deskew PLLs
• DLLs for high-speed DDR and other interface applications
• Low-jitter and very process tolerant
• Versatile, with wide output frequency and multiplication ranges (1-4096)
• small sizes and flexible form factors for easier integration

Deliverables

• available in TSMC, UMC and Chartered processes from 0.25µm to 65nm
• GDSII and LVS Spice netlists
• Behavioral, synthesis and LEF models
• extensive user documentation
• Integration support to ensure successful tape outs

True Circuits, Inc.
4300 El Camino Real, Suite 200
Los Altos, CA 94022
Telephone: 650.691.2500
Fax: 650.691.7606
timing@truecircuits.com
www.truecircuits.com/timing

InCyte from Giga scale IC

Fast and accurate Chip estimation

• reduce die size, power, and cost
• Compare different process technologies and Ip options
• package recommendations and pricing
• estimate final production chip cost
• rapid chip quoting

From specification to silicon
InCyte from Giga scale IC allows design teams to significantly reduce the risk, lower the power requirements, and minimize the costs associated with implementing chip designs. Because InCyte produces accurate and reliable estimations of die size, power, leakage, yield, and cost at the earliest stages of the design flow, the tool enables you to make informed decisions before expending valuable resources.

InCyte provides fast and accurate chip estimation at the architectural stage of the design flow. the tool lets you perform tradeoff analysis by visualizing a design across technology nodes, process variants and Ip libraries. users can make macro or micro modifications to their design specifications and immediately quantify their technical and economic impact upon the final chip. InCyte’s comprehensive economic analysis engine includes package recommendations and performs an estimation of final production chip cost. the tool also frees you from your forced dependence on outdated spreadsheet tools, since InCyte fully automates the critical architectural analysis and feasibility phase of the design cycle.

As an InCyte user, you enter your chip specification in an intuitive manner, and in just seconds you are viewing a visualization of your chip design, including an estimated floorplan, complete datasheet, and a comprehensive economic analysis. InCyte then facilitates rapid ‘what-if’ analysis between technology nodes, process variants, Ip options, and IC packages, thus allowing you to make the early, informed decisions that ultimately will result in lower power requirements and reduced risk, die size, and chip cost.

InCyte builds on designers’ strengths by helping them engineer lower cost, higher margin chips. the tool’s economic analysis engine recommends and prices a package, calculates wafer cost and chip yield, analyzes test & assembly costs, and produces an estimation of Nre costs. Its lifecycle analysis function lets you forecast chip cost over time, and return on investment (roI) analysis provides a realistic timetable for profitability on a design.

InCyte enterprise
InCyte enterprise can be fully customized to meet your corporation’s chip estimation and economic analysis needs, as well as to draw upon your internal process technologies and Ip libraries. It is a complete client-server system which operates within a corporate network, providing you with a local, chip estimation environment linked into internal Ip databases. a complete IC economic analysis can be performed with customized economic models.

Chipestimate.com
At www.Chipestimate.com, Giga scale IC makes available a no-cost version of InCyte that performs chip estimations based solely upon industry average foundry and Ip library data. InCyte Lite can be upgraded to include technology data from leading foundries and Ip vendors such as tsMC, uMC, arM (artisan), Virage Logic, and more, thus facilitating significantly more accurate estimations. upgrade subscribers can estimate designs in specific process variants with explicit Ip libraries, and compare a design across various foundry and Ip vendor offerings.

InCyte upgrades, available from Chipestimate.com, also feature a comprehensive IC economic analysis engine which generates accurate estimates of final packaged chip cost. please visit www.Chipestimate.com today. Giga scale Integration Corporation
10050 North wolfe road, suite sw1-266
Cupertino, CA 95014
USA
Telephone: 408.255.0444
www.GigaIC.com

Accelerate Forward with Poseidon Systems

Poseidon’s Tuner & Builder tools provide system designers with an integrated environment for design, optimization and acceleration of processor-based architectures. With Poseidon’s EDA tools, designers can increase performance, reduce power, shorten time to market, and reduce cost. Key applications include video, audio, wireless, and security.

Using Tuner, critical HW/SW routines and architectural inefficiencies are identified, greatly reducing development and optimization time. With Builder, the designer can easily generate a complete hardware accelerator system, drastically speeding up selected algorithms. The tools support ASIC and FPGA platforms with ARM, MicroBlaze, PowerPC, and Nios processors.

Visit our website and request our white paper, register for the DAC seminar, or visit us at DAC booth 126 hall B. Poseidon Design Systems
1081 Camino Ricardo
San Jose, CA 95125
USA
Telephone: 925.292.1670
Fax: 925.454.1959
www.poseidon-systems.com

PCI Express Integration and Verification

PCI Express is the third generation I/O bus used to interconnect peripheral devices in computing platforms. Its versatility and performance make it well-suited for server, workstation, desktop, mobile, and embedded applications. PCI Express is based on the industry-standard PCI bus and is backwards-compatible from a device driver point of view. But unlike the PCI parallel bus architecture, PCI Express is a high-speed, point-to-point serial connection (or “link”) between two devices utilizing a packet-based protocol. The performance of PCI Express is easily scalable by using up to 32 signal pairs, or “lanes”, to form a single link. By utilizing PCI Express switches and bridges, a complex fabric can be built up with many peripheral devices.

The complexity of PCI Express offers some unique integration and verification challenges. Guaranteeing correct operation of a PCI Express device requires randomized testing with high traffic volumes, as well as, directed tests that target specific conditions. Integre engineers have experience developing and verifying all aspects of PCI Express IP, integrating it seamlessly into large systems, and performing system-level verification. Our expertise includes:

•    Link Training (LTSSM) •    Power Management •    Error Handling

•    Transaction Model •    Quality of Service (QoS) •    Flow Control

Integre Technologies can help you integrate PCI Express IP into your design and provide a comprehensive verification environment for the entire system.

Once we size up a customer’s application, we work with the customer to develop an integration and verification strategy that will maximize the functional coverage of the system. We can then build up a highly-reusable verification environment using the latest tools such as Specman (Verisity) and PureSpec (Denali). After this environment is in place, we create a suite of randomized and directed tests that will cover the requirements of the verification plan. The fact that our verification engineers are also experienced RTL designers allows us to quickly zero in on subtle design and integration problems.

As PCI Express evolves, Integre Technologies will continue to provide quality verification solutions for a broad range of applications. We are committed to making bug-free PCI Express designs a reality. Integre Technologies
1160 Pittsford-Victor Road, Suite G
Pittsford, NY 14534
USA
Telephone: 585.292.1770 x200
www.integretek.com

Celoxica

Agility Compiler for SystemC
The Agility Compiler delivers SystemC behavioral design and synthesis, connecting TLM models to hardware for SoC prototyping and verification. The tool generates FPGA logic and RTL optimized for Design Compiler.

DK Design Suite
An EETimes Best Product winner, the DK Design Suite is a full ESL design environment for algorithm acceleration based on ANSI-C. DK supports system co-design and verification using C/C++/Matlab and RTL models, and delivers Handel-C synthesis to device-optimized FPGA and RTL.

PixelStreams
A current EETimes best product finalist, PixelStreams is a library of high performance parameterizable algorithm IP cores coupled with an easy to use block based graphical entry system. PixelStreams supports rapid prototyping and algorithmic design analysis for complex video and image processing systems.

RC Series FPGA Boards
Celoxica offers a collection of FPGA based development boards for embedded system prototyping and algorithm acceleration. The boards combine high density FPGA devices, soft-core & hard-core processors and an extensive array of peripherals. Integrated with Celoxica’s ESL tools and innovative APIs for embedded processor integration, the RC boards complete Celoxica’s system design realization environment

SoC Development Platform
By combining Celoxica & Toshiba design technology, Celoxica’s Toshiba MeP digital media SoC development kit provides a comprehensive package of software tools, hardware boards and utilities to help designers understand, evaluate, prototype and develop the Media embedded Processor into high performance system designs. Celoxica
66 Milton Park
Abingdon, Oxfordshire, OX14 4RX
United Kingdom
Telephone: +44 (0) 1235 863656
Fax: +44 (0) 1235 863648
sales@celoxica.com
www.celoxica.com

Programmable Digital Frequency Synthesizer (DFS) PLL

The Virtual Silicon DFS is the industry?s first Silicon Ready?, low-power, programmable delta-sigma fractional-N frequency synthesizer and features:

• Ability to support system clock as high as 3.0GHz
• Placability in the core or the I/O ring - Requires only four 40?m I/O slots including power pads and ESD (0.044mm2)
• Integrated macro requiring no external components
• Low cycle-to-cycle jitter of 15 ps p-p max at 800MHz for DDR2 application
• Programmability to generate any frequency with +/- 0.0 ppm accuracy from any crystal
• Deskew capability
• Available today in TSMC 130nm (CL013G, CL013LVOD) and 90nm (CLN90G)

Virtual Silicon
1322 Orleans Drive
Sunnyvale, CA 94089
USA
Telephone: 408.548.2700
Fax: 408.548.2750
sales@virtual-silicon.com
www.virtual-silicon.com

TimingDesigner

TimingDesigner is a flexible, interactive timing analysis and diagram tool. Its intuitive use of timing diagrams and patented spreadsheet technology allow users to model their unique timing challenges, analyze a range of conditions, and obtain accurate results. Designers can define timing constraints, evaluate timing parameters, create specifications, and analyze complex interfaces within their design. TimingDesigner 7.0 provides the ability to better manage growing design complexity by organizing the design into logical components within a single project. It also allows users to automatically merge designated component diagrams to greatly simplify the creation of interface timing diagrams.

The Chronology Division of Forte Design Systems
16150 NE 85th Street
Suite 214
Redmond, WA 98052
USA
Telephone: 800.800.6494
Fax: 425.869.4229
tdinfo@forteds.com
www.timingdesigner.com

Synplicity

The Identify® RTL Debugger is the first and only software tool that allows FPGA-based hardware designs to be functionally debugged directly from the RTL source code. Allowing designers to debug their hardware at the same level it was designed at dramatically reduces the time required to find hardware problems from weeks or months to days, providing significant cost savings and faster time to market. Unlike other approaches, the Identify software allows signals to be easily selected and results viewed directly in the original RTL source and in a waveform display.

Identify® Highlights

• Instrument and debug the design directly in RTL source code
• Incremental debug flow for Xilinx FPGAs
• Supports Verilog, VHDL, or mixed designs
• Export VCD or VHDL model to waveform viewers
• TCL-based command-line interface for scripting

Synplicity, Inc.
600 W. California Avenue
Sunnyvale, CA 94086
USA
Telephone: 408.215.6000
Fax: 408.222.0264
info@synplicity.com
www.synplicity.com

NEW from Summit Design

Vista™ Design Environment

• Provides hardware and software views to speed design and debug of SystemC applications
• Builds on familiar development tools including the OSCI simulation kernel, GCC compiler, GDB and Xemacs editor

To learn more about Vista and Summit’s other industry leading ESL solutions, send email to ESL@sd.com or visit www.sd.com.

Summit Design
2967 Michelson Drive
Irvine, CA 92612
USA
Telephone: 949.715.7561
Fax: 949.266.8732
ESL@sd.com
www.sd.com

Tuner & Builder

Poseidon’s Tuner & Builder tools provide system designers with an integrated environment for design, optimization and acceleration of processor-based architectures. With Poseidon’s EDA tools, designers can increase performance, reduce power, shorten time to market, and reduce cost. Key applications include video, audio, wireless, and security.

Using Tuner, critical HW/SW routines and architectural inefficiencies are identified, greatly reducing development and optimization time. With Builder, the designer can easily generate a complete hardware accelerator system, drastically speeding up selected algorithms. The tools support ASIC and FPGA platforms with ARM, MicroBlaze, PowerPC, and Nios processors. Visit our website and request our technology white paper.

Poseidon Design Systems
1081 Camino Ricardo
San Jose, CA 95125
USA
Telephone: 925.292.1670
Fax: 925.454.1959
www.poseidon-systems.com

Develop DFM Tools. Better. Faster.

SoftJin’s DFM Infrastructure framework, Nirmaan, is designed to jumpstart your DFM tool development effort. You can focus on developing the application while we handle the geometries. License Nirmaan and reach to your market faster!

• Efficient Layout data model optimized for DFM & other post-layout CAD application development
• Bundled with common geometrical & boolean operations and API’s for easy access to the database
• Hybrid hierarchy enabling multi-threaded, distributed computations
• Tight integration with GDSII, OASIS, OpenAccess 2.2

SoftJin is a customized EDA software development services company and has proven experience in developing complex customized EDA tools for its clients. Please visit www.softjin.com/DFM to find out more information on Nirmaan and free download of source code of GDSII/OASIS libraries!

SoftJin
2900 Gordon Avenue
Suite 100-11
Santa Clara, CA 95051
USA
Telephone: 408.773.1714
Fax: 408.773.1745
sales_us@softjin.com
www.softjin.com

cLGA® socket

InterCon cLGA sockets provide a solderless connection between chip and board. Our sockets are used in both high volume production as well as for test socket applications. Our patented BeCu contacts are being used in test applications requiring 1000+ cycles for test and burn in. Our fully automated production line allows us to build very high volumes of product with pricing below $.03 per contact in volume. Product is available on .050”cc and 1mm. Custom sizes and selectively loaded housings are available. Current sizes range from 50 position through 3800 position sockets

InterCon Systems
2800 Commerce Drive
Harrisburg, PA 17110
USA
Telephone: 717.540.5660
Fax: 717.540.5839
custserv@interconsystems.com
www.interconsystems.com

On-Demand Web Seminar Sponsored by Avnet Electronics Marketing

Cost management is one of the most important implementation considerations for a design manager. Join Doug Dreibelbis, IBM’s Senior Engineer in the ASIC Product Marketing group, for this one-hour Web Seminar hosted by Avnet Electronics Marketing as he discusses how to best manage the total cost of ASIC development and provides direction for how to minimize costs using the IBM approach.

Web Seminar topics include:

• Reducing the full cost of implementing a differentiated logic design through defect-tolerant library elements and assorted design automation tools
• Availability of analysis tools that permit the design team to predict timing accurately and to make important power/performance trade-offs
• Design aids that link the chip design/floorplan with the design of the chip carrier to minimize the amount of design effort, cost, turn-around-time, and risk
• Designing for manufacturing yield
• The benefits of variation-aware timing methodology

To register, visit www.em.avnet.com/asicwebseminar

Avnet Electronics Marketing
2211 S 47th Street
Phoenix, AZ 85034
USA
Telephone: 800.408.8353
customer.care@avnet.com
em.avnet.com