Published in issue of Chip Design Magazine

Focusing on Primary ESL Design Solutions

Early ESL design tools often failed to deliver on their promises, but designers and EDA vendors have carried on, and the electronics industry now has a stable of quality ESL tools to help conquer the design complexity issue.

In the not-so-distant past, design teams would often start a project by drawing the architecture of their system on the back of a napkin, assign functions to each block, and then start hand-coding each block in RTL. Once a physical prototype arrived, it was the software and firmware developers' job to code around the inevitable hardware deficiencies.

This approach worked well until relatively recently, when the complexity of advanced systems and time-to-market pressures combined to stretch RTL-centric approaches to the breaking point. Today's designs are too massive and complex to cost-effectively explore in RTL. The market will not tolerate extended product development cycles, the approach does not allow enough flexibility to efficiently achieve optimal hardware implementations, and software workarounds no longer deliver the required levels of performance.

These problems are driving designers to investigate new methodologies, namely electronic system level (ESL) design. ESL design addresses this complexity problem by elevating design to a higher level of abstraction, relieving designers from the overwhelming detail of low-level design. Initially based on vague promises, ESL design has become a cause célèbre in the EDA industry, drawing seemingly endless commentary on competing languages, methodologies, and usage models. Early ESL design tools often failed to deliver on these promises, but designers and EDA vendors have carried on, and the electronics industry now has a stable of quality ESL tools to help conquer the design complexity issue.

Today, ESL design for hardware has gravitated to two primary design pain points: design exploration and implementation. ESL exploration allows designers to create models with less effort and provides early visibility into the impact of architectural design decisions. Since designers can easily analyze different architectural options within a much shorter amount of time, teams can predictably achieve hardware designs optimized for size, performance or power, depending on the target application.

This step also provides a platform for early hardware/software validation. Traditional design flows require design teams to wait until hardware implementation – or even physical prototype – before hardware/software validation. Under the ESL model, designers can quickly validate partitioning schemes and specify changes while they are still relatively easy to make. In contrast, identifying architectural problems in RTL can take days of simulation time, implementing hardware changes may require weeks of effort, and still the process may not necessarily end with an optimal design.

As for the implementation phase, ESL capabilities can solve the designer's problem of transferring the insight gained during exploration to the traditional hardware and software flows. Some ESL tools today ignore the implementation problem, leaving designers to manually implement the optimized high-level architecture. This introduces a myriad of problems, from design misinterpretations that threaten to undo earlier architectural optimizations to hand-coded errors that can delay time to market. However, the most effective ESL implementation technologies eliminate these problems by generating high-quality RTL 10-to-100x faster than manual creation methods, and in a way that eliminates specification misinterpretations.

High-level synthesis has emerged as a cornerstone technology for ESL hardware implementation. Mentor Graphics first entered this segment in 2004 with the introduction of Catapult Synthesis, the first tool to automatically generate hardware from a pure ANSI C++ source. By starting with pure ANSI C++, Catapult can deliver the highest quality hardware, while delivering SystemC transaction-level models (TLMs) for system exploration. Adding ModelSim for SystemC, and users have a flow for rapid hardware implementation and verification, reducing months of hand-coding effort to hours and enabling hardware designers to focus on creating the best hardware for a given application.

The recent acquisition of Summit Design means that Mentor Graphics now owns an established product line for ESL exploration. Summit products, such as Visual Elite System Design, support the SystemC TLM methodology to provide system-level modeling and exploration capabilities. Again, this allows users to explore designs at the architectural level, where they can have the greatest impact on performance, power consumption, or size of a system. Ultimately, these products will enable convergence between the ESL and RTL worlds, providing design teams with the ability to find the optimal design architecture then rapidly implement into traditional design flows.

This transition to ESL is well underway. Looking back at the transition to RTL, we now realize that it took nearly 20 years to create complete design, synthesis and verification methodologies at that level of abstraction. However, with these new products, Mentor Graphics is the first EDA company to offer ESL solutions for design, synthesis and verification. With a growing customer base and the industry's most comprehensive offering of ESL tools, Mentor Graphics intends to make it easier for the industry to embrace the benefits of the ESL design domain. Simon Bloch has served as General Manager of the Design Creation and Synthesis Division at Mentor Graphics since 2002. Prior to Mentor he was the founder and served as President and CEO of Aristo Technology. Over the last 20 years, Simon has held senior positions in marketing, engineering and operations in EDA, IC and system companies including Compass Design/VLSI Technology, Daisy Systems, and Tadiran Electronics. Simon has a BSEE from Tel Aviv University majoring in microelectronics, computers, and medical engineering.