feature

Published in June 2008 issue of Chip Design Magazine

Cutting-Edge Application Demands Engineering Agility

Mobile-TV receiver becomes a reality using an algorithmic C++ synthesis environment to enhance design productivity.

The next major feature for consumer electronics is broadcast TV in hand-held devices. As mobile products become ubiquitous in all parts of the world, demand exists for accessing broadcast TV. Users want to view live, local sports, news or a favorite show at anytime and in any place— whether it is on their mobile handset, in the car, on a laptop or portable media player. This is especially true in urban areas where large numbers of people ride trains and public transportation to and from work. What could be better than watching the evening news while taking the metro home?

The goal is to deliver the same live, familiar programming on a handset that consumers already enjoy on their television at home. Until now, however, supporting mobile TV on handsets or portable navigation devices had proved elusive. Solutions were too powerhungry, could not deliver acceptable sensitivity for consumer acceptance, and did not support high-speed mobility. So the challenge remained: how to deliver mobile TV that could meet and exceed consumer requirements for performance and cost.

SINGLE-CHIP RF AND DSP SOLUTION FOR MOBILE TV

Recently, a solution has come to market that successfully addresses this challenge through innovative RF and DSP design. With support for both analog and digital broadcast standards, the single-chip
CMOS mobile TV receiver allows mobile device manufacturers to tap into an existing TV ecosystem and provide consumers with worldwide access to free, live, familiar programming, as well as emerging made-for-mobile content. Designed with consumer usage cases in mind, the mobile TV receiver provides exceptional reception and picture quality, even at high speeds in excess of 430 km per hour (265 mph). Equally important, the solution has ultralow power consumption, delivering extended viewing time.

ALGORITHMIC-INTENSIVE DESIGN

A collection of advanced algorithms and architectures form the technology foundation that enable the performance enhancements in both reception sensitivity and power consumption. These algorithms and architectures are directed at overcoming the real world impairments caused by motion, high speed, and variable signal strength. They not only enhance and optimize reception, providing error prevention and error concealment, but also enable the lowest power consumption possible. The reception optimization, combined with advanced Doppler and multi-path compensation
algorithms, lead to exceptional picture stability and color lock, even in challenging mobile reception environments.

Figure 1. The Konka D326 is one of more than 50 Telegent-enabled, freeto-air TV phones available on the market.

These advanced IC designs would have been challenging to produce using the time-honored, manual-intensive approach to algorithmic design. Using traditional methods, the system designer would capture the algorithm intent in ANSI C or C++ and then create testbenches to verify the algorithm behavior. The next step was to hand off the algorithms to hardware designers, who translated the algorithms into register transfer level (RTL) and then meticulously verified that the translation was exactly equivalent to the original C++ algorithm.

The system team then had to compare the RTL to the C++ model, verifying it with patterns to make sure the RTL faithfully captured the design intent. They needed to be sure that important nuances, like rounding and saturation, were not abstracted out during the coding of the RTL model. Creating HDL testbenches and running a full RTL verification that provided sufficient coverage was a very tedious and timeconsuming due to the many standards required for broadcast TV and the combinations of modes. The last step required taking the RTL code and running it in an FPGA environment for real-time prototyping, with the eventual goal of mapping it to an ASIC for volume production.

DRAWN TO A HIGHER LEVEL OF DESIGN

To overcome the limitations of this traditional approach, design teams can adopt cutting-edge design methodologies to help them deliver extremely challenging design into high-volume production within very tight schedules. Since critical portions of the design are DSP-based, these design teams are especially interested in emerging ESL (electronic system-level) capabilities, focused on streamlining algorithmic-based design creation.

Figure 2: Telegent's TLG1120, a single-chip mobile TV receiver enabling free-to-air mobile TV in cellular phones and other portable devices.

Algorithmic C++ synthesis is thus of special interest because it offers a significantly more efficient design process. An ESL design flow raises the level of abstraction from the RTL-level to the system-level. Working at the system level gives design teams greater flexibility, improved verification, and reduced design time. An ESL design flow has the same initial starting point with the system designers: using ANSI C++ to model the system and develop algorithms. Instead of manually creating the
RTL, however, the original ANSI C++ algorithm is used for hardware implementation, leveraging a new wave of system-level tools based on algorithmic C++ synthesis. Automating this step can save literally weeks, if not months, of engineering time.

Since the generated RTL is correct by construction and preserves the system designer’s original algorithm intent, it is much easier to verify. Formal equivalence checking is used throughout the process to keep code refinements in sync with the original C++ model, and to comprehensively verify that the RTL functionality matches the C++ code. The testbench created in C++ can be directly re-used for verifying the RTL, eliminating the timeconsuming creation of an HDL testbench.

THE ROAD TO HIGHER-LEVEL SYNTHESIS

To assess the effectiveness of C synthesis, Telegent Systems, a fabless CMOS semiconductor company focused on mobile TV receivers, first performed an evaluation comparing their existing RTL design approach with synthesizing the  same block directly from an ANSI C++ algorithm. After examining several competing Algorithmic C++ synthesis solutions, they chose the Mentor Graphics Catapult® C Synthesis environment to automatically synthesize their ANSI C++ algorithms into RTL implementations.

The results far exceeded the team’s expectations. The area of the block generated with C++ synthesis was quite close to the original block and eliminated issues with timing despite
the addition of several new features. Even though the C++ model had been fully verified and that RTL from Algorithmic C++ synthesis is correct by construction, they still performed some initial block level verification leveraging the automatic SystemC verification environment generated by the synthesis
environment. They found the SystemC output extremely useful because it allowed automatic synchronization between the original C++ testbench and the generated RTL.

What surprised the team the most was how easily it was to incorporate algorithm refinements. On previous projects, non-trivial resource and time would be needed to add a new algorithm feature, verify it, and then take it to prototyping. In comparison, using algorithmic synthesis, changes were completed faster with fewer engineering resources than expected. The team could then quickly and successfully port the block to the FPGA environment. Overall, it was possible to reduce the design cycle for some blocks by 70-80%.

MAINSTREAMING ALGORITHMIC C++ SYNTHESIS

Impressed with the initial outcome, the design team decided to incorporate algorithmic C++ synthesis into their existing ASIC design flow. They focused the algorithmic synthesis effort on four blocks that support the DSP algorithms. With an eye on future reuse, the systems designers have written the
initial C++ code so it can be easily reused in later design. This requires understanding how to express hardware detail in C++ code while maintaining fast simulations and using a technique called “object oriented hardware,” very similar to reuse methods used by software engineers for the past decade.

To that end, the design team relied on Algorithmic-C (AC) data types developed by Mentor Graphics that faithfully represent hardware fixed precision semantics such as truncation, rounding, and overflows. Taking advantage of the extensibility of C++, the designers created a complex number container class to support the design's signal processing. Using AC data types minimize the chance of introducing errors during numerical refinement while maintaining simulation performance. AC data types have become the new de-facto standard for arbitrary size integer and fixed-point arithmetic [and are freely available from mentor.com http://www.mentor.com/products/esl/high_level_synthesis/ac_datatypes.cfm.] In addition, writing code that leverages ANSI C++ techniques like templatization, classes and specialization allows completely reusable and parameterizable hardware previously not achievable with RTL methods.

System and hardware designers alike had to undergo a learning process to incorporate algorithmic C++ synthesis, but the transition was minor, and the results definitely justified the effort. For the system designers, higher-level synthesis frees them from having to oversee the details of the RTL creation to ensure the code captures their design intent. Confident that the synthesis is accurate, they can instead focus their efforts on development of next-generation algorithms. As for the hardware designers, they like the fact that fully functional RTL can be generated in a few hours, and subsequent evaluation and iterations can be done in much less time. Now the designers can do more experimentation on algorithms and architecture, exploring alternatives in just hours or days, rather than weeks.

FUTURE ASPIRATIONS

This experience with algorithmic C++ synthesis has convinced the design team that it is an effective approach for future designs. Higher-level synthesis will make it viable for them to continue to be productive on aggressive schedules with their existing engineering resources. In fact, the experience has been so positive that they plan on doubling or tripling the number of blocks they synthesize directly from the C++ models in their next generation design. Another added benefit is that the “golden source code” is technology neutral ANSI C++, making it easy to retarget their future designs.

The end result is a significant productivity boost for the design organization. And for consumers, it means more technology innovation for providing live, free television access to millions of people worldwide.

Dr. Andy Burstein – Dr. Andy Burstein is Vice President of Engineering at Telegent Systems, where he leads the engineering team in the design and development of high-performance single-chip solutions for enabling mobile TV in handheld devices. Dr. Burstein received his M.S. and Ph.D. degrees in Electrical Engineering from the University of California at Berkeley and holds numerous patents.