Published in issue of Chip Design Magazine
Consumer Electronics are changing the face of DRAMs
In order to "future-proof" current SoC designs in 2007, DDR3/DDR2 IP cores started to roll out in early 2007. These cores will allow SoCs to interface to either DDR3 or DDR2 SDRAMs, providing key flexibility to the end SoC and its customers.
The processing required in the SoCs at the heart of modern consumer products requires large buffers that are not economically feasible on the same die as the SoC. The largest growth area for SoCs that require off-chip DRAM storage is the video and media processor market driven by fixed pixel panels (e.g., Plasma & LCD) and video CODECs as applied in the high definition TV markets.The mainstream DRAM components in 2007 will be 512 Mb or 1 Gb DDR2 SDRAM, with maximum data bandwidth of 800 Mbps per pin. DDR2 SDRAMs were designed for optimal performance in a PC, so it is no surprise that the interface is complex and daunting to the typical SoC design team. Fortunately, IP core providers supply silicon-proven memory controller and interface IP cores that can be licensed by SoC developers for less than it would cost to internally develop such an interface and with much less risk.
What makes matters are made worse is that complex SoCs take years to develop and bring to market and then they can stay in the market for several years, even in the consumer electronics market. While DDR2 is the highest volume and least expensive (per bit) product today, in 3 to 5 years it will be replaced by DDR3 SDRAM. The new features in DDR3 standard now being developed by JEDEC build on the DDR2 SDRAM feature set and add logical improvements to increase system bandwidth (up to 1.6 Gb/s per pin) and reduce power consumption.
For the transition from DDR3 to DDR2, the internal speed of the DRAM core is largely unchanged. Therefore, in order to permit the 1.6 Gb/s DDR3 bandwidth target that is twice that for DDR2, DDR3 uses a pre-fetch of 8 words versus DDR2's 4 word pre-fetch. Thus, for every read or write operation, a total of 8 words are accessed in the core of the DRAM to keep up with the data rate at the pins. This requires the use of the DDR3 "8n rule" which states that a new column command can only be issued on every 8 clock edges or on every 4th rising clock edge. As was the case with DDR2, DDR3 SDRAMs support programmable burst lengths of 8 and 4 but when using a burst length of 4, the 8n rule must still be followed. In this case, back-to-back reads or writes will have gaps between the bursts of data to obey the 8n rule. To somewhat offset this situation, DDR3 introduces a burst chop command to allow on-the-fly selection of burst length = 4 or 8.
Packaging technology for DRAMs has finally improved to the point where it is no longer a pin limited package. The Ball Grid Array (BGA) packaging for the DDR3 SDRAM allows for more pins than is needed by the device – a luxury that was unheard of in the 1980s and 1990s. This has finally facilitated the addition of an asynchronous RESET pin for DDR3 SDRAMs. Long desired by the DRAM vendors, this pin will finally guarantee that the state machine inside the chip can be reset to a known state after power-up.
In order to provide for more robust system operation, the DDR3 SDRAM also improves the output driver to PCB trace connectivity. DDR3 SDRAMs include a ZQ pin that is connected to an external precision resistor that is used to precisely adjust the "on" impedance of the output drivers and the on die termination (ODT) impedances. DDR3 SDRAMs optimize the output driver and termination impedance such that mismatch to the PCB trace impedance is minimized thus minimizing reflections that create ringing on the signals. The ZQ pin plus external resistor also provides for significantly better controlled impedance values with much tighter tolerances as compared to those built with simple on-chip resistors (in series with transistor switches) as used in DDR2 SDRAMs which can vary by ±20%. Use of the external precision resistor also reduces the impedance variations due to process, voltage and temperature variation. The DDR3 SDRAM specifies both a long calibration sequence to be used after power-up and a short recalibration sequence that can be used to periodically recalibrate the impedance values during normal operation as voltage and temperature drift.
By matching the impedance of the driver close to that of the PCB trace, the impedance discontinuity is greatly reduced resulting in smaller signal reflections. Reducing these signal reflections results in a better data eye and improves the timing budget for the memory channel. Figure 1 shows the typical effect of signal reflections resulting from impedance mismatches. These reflections, while not a significant problem in DDR2, become more of a problem in DDR3 due to the higher clock speeds and the more limited output swing owing to the 1.5V VDDQ supply as compared to DDR2 that operates with VDDQ = 1.8V.
To further improve signal integrity on the data bus, DDR3 SDRAMs also introduce a dynamic ODT function that permits the termination impedance of the DDR3 SDRAM to be varied between two preset values on-the-fly without issuing a mode register set command.
Figure 1: DDR SDRAM Data Eye Showing Impedance Mismatch Ringing
In order to reduce the module affects on signal integrity in computer systems, DDR3 memory modules (DIMMs) adopted a "flyby topology" for the addresses, command and clock signals. Instead of a more common star topology, the fly-by topology buses signals to the side of the module and then across the chips in a linear fashion (refer to Figure 2). The fly-by topology offers performance benefits from reducing the number of stubs and their length but causes flight time skew between clock and data/strobes at every DRAM as the signals traverse the DIMM. This makes it difficult for the controller to maintain the relationship between the data and data strobes relative to the clock. Therefore, DDR3 controllers should support 'write leveling' with DDR3 SDRAMs to compensate for this skew as shown in Figure 2. However, for those situations where an SoC with a DDR3 SDRAM interface connects to <= 4 memory chips, write leveling is not required in the system.
DDR3 SDRAMs include a new multi-purpose register (MPR) that is primarily used to output a predefined data pattern for initialization purposes. By using the MPR, DDR3 SDRAMs can output data to the memory controller without any requirement for a previous write operation. The MPR allows the memory controller PHY to calibrate the timing for read operations by optimizing the timing circuits that shift the data strobes into the middle of the data eyes. Once read operations are fully calibrated, write timing calibration, if required, can be performed by traditional write data, read data, compare to expected data sequences.
Figure 2: DDR3 DIMM Fly By Topology Requiring Write Leveling
DDR3 SDRAMs build upon a low power option for self refresh mode introduced with some DDR2 devices that takes advantage of operating temperature awareness. The principle behind this feature is the inverse relationship between the memory array temperature and the rate at which the DRAM cells leak (higher temperature results in more leakage and shortens the required refresh interval). DDR3 SDRAMs have two self refresh modes that scale the refresh rate according to temperature.
If the case temperature of the DDR3 SDRAM is below 85° Celsius, the chip can use a 7.8 us refresh interval. However, if the DDR3 SDRAM is between 85°C and 95°C, the chip must use a nominal 3.9 us refresh interval which is also the only rate available with DDR2 SDRAMs that operate up to 95°C. Since the DDR3 SDRAM will likely cool off in self refresh mode, the ability to slow down the refresh rate and conserve almost one half the power is a huge bonus to standby power sensitive applications. For DIMM applications, the thermal sensor is likely to be found in the support silicon on the DIMM. Some memory vendors may also elect to put an on-die thermal sensor on the DDR3 SDRAM itself.
Table 1 provides a comparison of the major features of all JEDEC SDRAMs from the first SDRAMs (also called PC100 and PC133 SDRAM) to DDR3 SDRAMs. Table 1 highlights a few of the other changes for DDR3, most notably the manner in which the various latencies are programmed.
Table 1: Feature Comparison of JEDEC SDRAMs
DDR3 prototypes were announced over a year in advance of the completion of the JEDEC standard that is yet to be published as this article is written. Most if not all of these parts are not 100% compatible with the JEDEC standard and were intended for the initial debug of prototype or experimental PC motherboards and will be replaced in the market with newer JEDEC standard DDR3 SDRAMs.
Outside the mainstream computer market, DDR3 will not be a cheaper option compared to DDR2 until 2010. Any serious offering of DDR2-1066 has the potential to delay DDR3 adoption even further until the memory vendors can yield suitable volume of the DDR3-1333 components. Fortunately, in order to future-proof current SoC designs in 2007, DDR3/DDR2 IP cores will be rolling out in early 2007. These IP cores will allow the SoC to interface to either DDR3 or DDR2 SDRAMs, providing key flexibility to the end SoC and its customers. Jody Defazio joined MOSAID Technologies in July 1995. During his 12-year tenure at MOSAID, he has held several positions including IC Design Engineer, Design Manager, and his current position as VP of Engineering for Semiconductor IP. Jody holds 3 patents both issued and pending.