1. Editor’s Note

I hope I never find out that an FPGA is responsible for runaway hybrids. But the world is rapidly becoming a universe of embedded systems, and FPGAs are becoming stars. Dave Orecchio, CEO, GateRocket, Inc. starts us off with a quick seminar on fault-finding in Device Native Verification: Improving Visibility to Address the Growing FPGA Debug Crisis. Next I first became curious about what Infinisim was doing when I read about its mixed-signal simulator verifying the functionality of programmable chips. My curiosity led to sharing Drew Plant’s viewpoint on The Accuracy Requirement for Timing Closure in Advanced-Node Designs. Then keep paging down as we dive into our regular features including an invitation to help your career survive and thrive in our Showtime section.

To see our additional newsletters please visit: www.chipdesignmag.com/enewsletters/

2. Viewpoint Exclusive

Device Native Verification: Improving Visibility to Address the Growing FPGA Debug Crisis

By Dave Orecchio, CEO, GateRocket, Inc.

Using an advanced design methodology to develop modern FPGAs is a requirement for today’s leading-edge programmable devices. RTL-based design, synthesis and place-and-route are all standard tools in the designer’s toolbox. But as FPGAs become more complex, the traditional blow-and-go and debug in the lab methodology is no longer a sufficient debug methodology as it was for simple programmable logic devices.  Old style lab debug approaches are the primary cause of project delays. You choose the FPGA device for its time-to-market and flexibility advantage, only to see those advantages washed away in the endless lab debug cycle. 

For example, full-chip logic synthesis and place-and-route (PAR) runs that used to complete during lunch can now reach 18 to 24 hours. This means that when a bug slips through to the system test lab and requires a change to the FPGA design, it can take more than a day to get the device re-programmed with a fix ready for testing. The problems are only exacerbated by the fact that a simulation run of the full-chip RTL that once completed in hours can now take many days as well. The temptation to solve problems by iterating through the RTL-to-programming cycle and debug in the lab runs into the reality that these steps each take many hours or days to complete each time they are run. Thus, the time-to-market productivity gained by re-programmability can quickly disappear.

Full Story >> http://www.chipdesignmag.com/display.php?articleId=4069

Send your comments to jkobylecky@extensionmedia.com and our Editorial Director at jblyler@extensionmedia.com.

3. Viewpoint Exclusive:

The Accuracy Requirement for Timing Closure in Advanced-Node Designs

By Drew Plant, Infinisim

Designers who rely on timing verification flows that worked well for older process nodes are facing a paradigm shift. Industry leaders have already announced production designs at 28nm, where designers will find themselves tackling flow and tool questions to address new challenges imposed by the complexities of the new process.  Lack of accuracy in static timing analysis is an important challenge for advanced-node designs as highlighted in a recent article http://chipdesignmag.com/display.php?articleId=3790. As mentioned in that article, absolute uncertainty in timing delays increases due to (among other things) non-linearity of delays with respect to process variations.

The smaller gate delay and size in 28nm carry the advantages of faster clock rates and higher density.    The penalties for faster clock rate are increased dynamic power and reduced timing margin.  In particular, timing uncertainty as predicted by the static-timing-based flows commonly in use today will result in unachievable timing budgets at the 28nm process node.  The issue of shrinking timing window is illustrated for setup timing in the following figure.

Full Story >> http://www.chipdesignmag.com/display.php?articleId=4068

4.  News:

High-bandwidth, Lower-power 28-nm FPGA Family

Altera Corporation announced its next-generation 28-nm Stratix V FPGA family, the industry’s highest bandwidth FPGA. Offering up to 1.6 Tbps of serial switching capability, the FPGAs leverage a myriad of new technologies and a leading-edge 28-nm process to reduce the cost and power of high-bandwidth applications. The FPGAs provide up to 1.1 million logic elements (LEs), 53-Mbits embedded memory, 3,680 18x18 multipliers and integrated transceivers operating up 28 Gbps. The devices also incorporate application-targeted hard intellectual property (IP) for increased system integration and performance without the cost and power penalty. The family includes four variants that address a broad range of applications in the wireless/wireline communications, military, broadcast, computer and storage, test and medical markets.

Altera >> www.altera.com

5. News:

Prototyping with Pre-tested IP and Advanced Verification

Synopsys, Inc. introduced its HAPS-60 series of rapid prototyping systems--a comprehensive solution for complex SoC design and verification challenges. Part of the Confirma Rapid Prototyping Platform, it is billed as an easy-to-use and cost-effective rapid prototyping system for early hardware/software co-verification and system-level integration at near-real-time run-rates, using at-speed, real-world interfaces. Built with Xilinx Virtex-6 devices, the series combines performance, capacity, pre-tested IP and advanced verification functionality. Key features include: clock frequencies of up to 200MHz; support for real-time interfaces such as video, cellular data or live network traffic; and full system integration and testing of all hardware and software in a real-world environment.

Synopsys, Inc. >>>> www.synopsys.com/

6. News:

Development Kit Accelerates PCI Express System Design

Lattice has a new low cost PCI Express development kit for its LatticeECP3 family of low power FPGAs. The new kit features four key capabilities. First, the kit enables users to bring up running PCI Express hardware in thirty minutes or less. Second, various demos included in the kit address control plane through data plane performance requirements. Third, source files for the demos are available that enable rebuilding designs up to a known good starting point. Finally, the kit enables a rapid transition to design exploration through the included software tools, IP enabled evaluation process and project source directories.

Lattice Semiconductor >> www.latticesemi.com

7. News:

RMM Library and FPGA Primitive Support Added to Rule Checking

Aldec Incorporated revealed its latest Design Rule Checking application, ALINT 2010.02. The release adds support for Reuse Methodology Manual (RMM) design rules that define a methodology for efficient reuse and verification of System-On-A-Chip (SoC) designs. Altera and Xilinx FPGA vendor primitives are now supported to enable accurate design rule checking on the latest FPGA devices. The latest release includes advanced technology enabling detection of all the levels of RTL design issues – starting from comparatively simple naming conventions and design structure to advanced topics such as reuse, optimal synthesis, power and area consumption, Design-For-Test (DFT), and Clock Domain Crossings (CDC).

Aldec >> www.aldec.com

8. News:

IPMC and Carrier IPMC BMR Starter Kits with Mixed Signal FPGAs

Pigeon Point Systems (PPS), an Actel company, announced new AdvancedTCA (ATCA) IPM Controller (IPMC) and ATCA/AdvancedMC (AMC) Carrier IPMC Board Management Reference (BMR) Starter Kits using Actel’s new SmartFusion intelligent mixed signal FPGA. The device integrates an FPGA, hard ARM Cortex-M3-based microcontroller subsystem (MSS) and programmable analog, offering full customization, IP protection and ease-of-use. The solutions can accelerate customer design cycles and enable designers to concentrate on differentiating their ATCA board products (including those with AMC slots) instead of expending internal effort meeting management requirements for xTCA specification compliance. Due to the built-in flash FPGA; IP blocks can be added to the FPGA to provide management focused functionality, eliminating the need for a separate PLD device.

Pigeon Point Systems >> www.pigeonpoint.com

9. News:

University of Regensburg Launches the World’s Most Power-Efficient Supercomputer

Xilinx, Inc. has had a major role in developing QPACE; a bespoke supercomputer developed to unlock the mysteries of Quantum Chromodynamics. The predominant simulation process used to model Quantum Chromodynamics is known as Lattice QCD and is only possible using high-powered, highly parallel supercomputers. Xilinx Virtex-5 LX110T FPGAs were selected to provide core networking technology in QPACE, a two-year project that required leading-edge performance from commodity components. Using a custom-design approach has made QPACE one of the most power efficient supercomputers ever developed, with a peak performance in single/double precision of 26/56TFlops and an average power consumption of 29kW per rack. This puts QPACE at the top of the Green 500 list; a league table for the world’s most energy efficient supercomputers.

Xilinx >> www.xilinx.com/

10. Showtime:

More Than Core Competence....What it Takes for Your Career to Survive, and Thrive!

"You do a good job. You take your work seriously. That should be all it takes for career success, right?  If you think so, you need a wake-up call!”

You are invited to a new and different career seminar at the 47th Design Automation Conference (DAC), Monday, June 14th, 2010 from 11:30 am until 2:00 pm. It’s for both men and women; in the electronics and EDA industries, as well as academia. There will be a keynote by Patty Azzarello, founder and CEO of Azarello Group, and author of  the new book “Off the Org Chart” www.azzarellogroup.com, and she’ll be backed by a panel of top EDA professionals.

Free attendance with advance registration, thanks to the generous support of sponsors: Atrenta, Axiom Design Automation, ClioSoft, EVE, Jasper Design Automation, MP Associates, Mentor Graphics, Real Intent, SpringSoft, and Synopsys. It even includes lunch!

Organized and supported by: Women in Electronic Design (WWED) formerly WWINDA, the DAC Executive Committee, ACM/SIGDA, CEDA, and the EDA Consortium.

11. In–Depth Coverage Links

Separation of C Synthesis Tools

SoC and FPGA design teams around the world are taking a serious look with regard to deploying tools to automate the creation of hardware from C/C++/SystemC. Simon Napper takes a look at how the search for productivity has become a driving force for change.

Full Story >> http://chipdesignmag.com/display.php?articleId=3487

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Exploiting Uniqueness of FPGA Silicon for Security Applications

Mandel Yu expands FPGA application areas by introducing a new class of primitives – Soft PUFs. By exploiting the uniqueness of FPGA Silicon and by incorporating a circuit to extract “silicon biometrics,” FPGAs can be used for unclonable security-oriented applications not possible before.

Full Story >> http://chipdesignmag.com/display.php?articleId=2899

12. Happenings Conferences

ESC Silicon Valley
McEnry Convention Center, San Jose, CA USA
April 26-29, 2010
http://esc-sv09.techinsightsevents.com/

5th Annual Multicore Expo
(held in combination with ESC Silicon Valley)
McEnery Convention Center, San Jose, CA USA
April 26-29, 2010
http://www.multicore-expo.com/

ChipEx2010
Convention Center, Airport City, Israel
May 4, 2010
www.chipex.co.il/eng/htmls/home.aspx

Semicon Singapore 2010
Suntec, Singapore
May 19-21, 2010
http://www.semiconsingapore.org/index.htm

2010 IEEE International Interconnect Technology Conference
Hyatt Regency San Francisco Airport Hotel, Burlingame, CA USA
June 7-9, 2010
http://www.ieee.org/conference/iitc.

IEEE International High Level Design Validation and Test Workshop 2010
Anaheim Convention Center (co-located with DAC 2010)
June 10-12, 2010
http://www.hldvt.com/10/

47th Design Automation Conference (DAC)
Anaheim, CA USA
June 13-18, 2010
www.dac.com

5th Annual Workshop on Architectural Research Prototyping
Saint-Malo, France
June 19, 2010
http://www.eve-usa.com/warp2010/

ACM IEEE International Symposium Computer Architecture
Saint-Malo, France
June 19-23, 2010
http://isca2010.inria.fr/

SEMICON West 2010
Moscone Center, San Francisco CA USA
July 13-15, 2010
http://www.semiconwest.org/index.htm

SEMICON Russia 2010
Expocenter, Moscow, Russia
July 14-16, 2010
http://www.semiconrussia.org/SCRUSSIA-EN/index.htm

Get your organization’s conference on the list. Send information to jkobylecky@extensionmedia.com

PROGRAMMABLE LOGIC DEVICE DESIGNER e–NEWSLETTER CONTACTS

Editor: Jim Kobylecky, jkobylecky@extensionmedia.com
Editorial Director: John Blyler, jblyler@extensionmedia.com

Advertising/Sponsorship Opportunities: Karen Popp,
kpopp@extensionmedia.com

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