ChipEstimate has savvy marketing and knows how to draw a crowd at DAC:

1) Get a big booth

2) Announce an iPad give away

3) Repeat often

Drawing for an iPad at Chip Estimate

What do cars have in common with EDA?

Well, nothing really, however this booth of IC Manage gets the Coolest Car award from me:

Coolest Car at booth of IC Manage

Who
Jerome Toublanc, Principal Product Engineer at Apache Design Automation

Overview

Notes
PathFinder – ESD integrity for advanced electronic circuits

What is ESD?

ESD for an IC at an IO pad. How do you protect your IC layout?

Failure – breakdown of interconnect, junction or gate oxide.

Protection – ESD protection, clamp cell. Make the discharge go through a known path. Placement of ESD cell is critical for safety.

History – At 180nm device channel heating during ESD discharge, at 65nm will gate oxide break, at 32nm and lower what is metal reliability?

Metal Reliability – amps per cross area. At smaller nodes the lifespan can decrease.

Three ESD models – Human Body Model (HBM), Machine Model (MM), Charged Device Model (CDM). Different classes per model: HBM Class 0 thru 3B, MM class M1 thru M4, CDM Class C1 thru C7.

Goals – perform ESD analysis early before tape-out, optimize my circuit, predict failures, minize overdesign

Approaches – engineering guidelines, visual plot checks, ERC (circuit netlist verification)

PathFinder Inputs – uses layout, technology plus rules.

Outputs – Pass/fail checks for HBM, MM, CDM

Layout based analysis:

-          HBM/MM – bump2bump, bump2clamp

• Example: 18 million instances, 702 power pads, 38 power domains, 2.5 hours run time
• Resistance network for VDD/VSS has to be extracted (same extraction engine as other Apache tools)

-          CDM – static, dynamic

-          EM – current density checks

Totem (block level, transistor level) or Redhawk (full chip) tools – can call PathFinder

Layout Based Analysis and Debug – IC layout that can be clicked on, see the ESD rule check results, display of the ESD path highlighted.

CDM Event Modeling – path between the die and the clamps. Tool has to compute all paths between VDD and VSS. Is the loop resistance below my threshold? Idenitfy logic cell to clamp cell discharge paths, compute arc resistance, compute loop resistance.

Current Density Check for ESD Events – Current density plot, EM plot. Highlights any rule violations so that you can go back and fix the nets.

-          Example: 17.35M, Nodes 133.85M, #clamp instance, 83, 5 hour run time, 54GB of RAM needed.

Transient Simulation based sign-off validation for CDM

-          Built-in extraction engine (on die RLC, package RLCK/S-param, include substrate RC network)

-          Proprietary modeling methodology

-          High voltage modeling

-          Clamp snap-back profile

-          SPICE accurate simulation technology (propriety simulation engine, transistor level capacitance modeling)

-          Layout based debugging GUI (cross probing, what if analysis, devices failure reporting)

-          Today the have a transistor level flow. A higher capacity cell-level flow is under construction.

Analysis Flow – setup and load design

-          Extract PG RLC, substrate network

-          Connect package netlist

-          Perform simulation

-          See the discharge voltage as a function of time

Prediction of ESD layout needs – how to do early planning and prototyping?

1. Define your floor plan
2. Predict block capacitance (CDM)
3. Define your PG grid
4. Define the PG pads
5. Explore clamp placement
6. Verify current density limits (visual rainbow plot on the layout)

Conclusions

PathFinder – ESD verification for early and sign-off design stages

• Prediction of ESD protection needs
• Full-chip multi-domain analysis capability

Q: how does the Calibre PERC approach compare to this?

A: not really sure of their capabilities.

Q: If you are testing Pad to Clamp and the Clamp has many fingers, do you handle that?

A: Yes, we do.

Q: Any correlation between your analysis and silicon measurements?

A: It’s kind of early to say. MoSys wrote a paper, “Reliability and mitigation of ESD induced failures for Advanced IP Designs”

Q: Any use of multi-core?

A: Yes, during some of the simulation can use mult-core.

Q: Any convergence issues?
A: Some early on but all resolved.

Q: What are the simulation result outputs?

A: Currents plotted graphically and numerically. Probe the current and voltage along any path.

Q: Do you support inductors in the modeling?

A: Yes, we simulate inductors for dynamic.

CK Lee, Yong Dai

CK Lee, CEO of CyberEDA

History – Epic, Synopsys, Nassda, Synopsys

Analog Design Debugging System (ADDS) – Helps IC designer to find bugs, RC values, compare simulation results.

-          Still in beta stage right now

Yong Dai, President of China branch (PhD EE, Cadence, Synopsys)
PCSIM – Parallel Circuit SIMulator

-          True SPICE simulator without Fast SPICE approximations (sounds similar to Berkeley Design Automation)

-          10X faster than SPICE when using 8 CPUs, 3X faster than SPICE using 1 CPU

-          Millions of devices capacity (2 million MOS, R, C customer netlist even on 1 CPU)

-          Better than SPICE accurate mode

-          User friendly interface

PLL example – PCSIM results looks like competitor most accurate mode

Customers – Located in Taiwan.

Pricing – $25K for a one year license

OS – Linux (Red Hat, SUSE), Windows

Who
You-Pang Wei, President of Legend Design

MSIM – SPICE simulator for IC and PCB, IBIS verification. Able to simulate RF, Std Cells and LCD (using Hybrid models). Measured data can be used to correct deficiencies in standard SPICE models. Used by the memory characterization tool mostly and can be used stand alone.

Turbo MSIM – Fast SPICE circuit simulator and can also use the Hybrid models. Co-simulates with Verilog A, good for Flash memory designers and LCD designs. Handles hierarchical designs. Example of SRAM with 50,546,176 MOS devices took 99 seconds to complete a transient analysis. Benchmark results show about 3X faster speed and same accuracy as other FastSPICE simulators.

Customers –CPU Company (Taiwan), most of the memory characterization companies. Silicon Library Technology (Japan). Conexant (US), Large Chinese Telecom company, Korean Foundry.

Multi-Thread results – 1 thread is 319seconds, 8 threads is 57 seconds (5.6x). No up-charge for mult-threading.

Pricing – MSIM starts at $15K for 3 year lease, Turbo MSIM starts at $100K for 3 years.

Models supported – Verilog A, CMI, TMI, LCD, S-parameters

Input netlists – HSPICE, Eldo, Spectre

New feature – Matrix Solver Selector, run this on designs with many RC elements and get 14X speed up and 2.6X less memory usage.

RC Reduction – built-in feature to reduce run times from 12.2X to 30X for extracted netlists. Accuracy is within 1% of un-reduced results.

Subcircuit SPICE models – supported for 65nm and smaller nodes. Reasonable RAM usage with subcircuit models.

MSIM Design manager – Show your schematics, control the simulation, view the results, manage test bench.

Buzz in the OVM UVM Booth

Crowds of engineers were interested in OVM and UVM this year at DAC.

3D glasses to lighten us up

TSMC and ST presenters

Winner of 10th annual Tensing Norgay Interoperability Award: IEEE ISTO

Overview
For the past several years I’ve seen TSMC create the iPDK standard and seen modest adoption, then along comes Si2 with OpenPDK. Are iPDK and OpenPDK complimentary, competitive, or what?

The ST speaker says complimentary, however when I talk with some CAD managers and EDA execs the two standards sound conflicting and over-lapping.

Notes

Vincent Varo (ST) – Design Kit Manager, Central CAD. Open PDK board member.

ST’s Vision on OpenPDK and iPDK concepts.

Goals – to produce openness and industry standard formats, be more efficient.

Single PDK to support and EDA vendor tool.

iPDK and OpenPDK are complementary approaches.

Adoption requires: collaboration between EDA, foundry, users

Need advanced technologies: 28nm, 20nm

Best in class tools mixed together that need standards.

ST PDK: OpenPDK & iPDK

OpenPDK: Foundries, EDA Vendors, Customers, PDK Development Team

Inputs: eDRM, eDevice spec, eModels.

Ouptuts: DRC, LVS, Tools, Libs, PEX, Spice models

iPDK: iDRC, iLVS, Tools, iLib, iPEX, Spice models

The iDeck can be interpreted by an CAD tool itself

Interoperable device library (normalized OA symbol, layout pcell generators,…)

An iPDK can be made of an OpenPDK standardized spec and recommendation.

OpenPDK from a CAD vendor viewpoint: input (eDRM, eDevice spec, eModels) -> Automatic development tools, OpenPDK, automatic validation tools, validation report.

Foundry view of OpenPDK – they create the normalized and standardized e Design Manual, e Device Spec

ST will support both OpenPDK and iPDK. Use OA as universal data storage. Not vendor specific, not foundry specific.

Priorities – eDRM definition as a reference, PDK input standardization for best in class automation flow. Make 28nm and 20nm iPDK and OpenPDK.

S.T. Juang (TSMC) – Sr Director, Design Infrastucture Marketing

TSMC Open Innovation Platform (OIP) – collaboration between, EDA, IP, services.

iPDK, iRCX, iDRC, iLVS, iPRT, iSNA, iSDK/TMI, unified DFM engine, unified IP specs

Design kit innovation –

AMS Reference flow: 28nm, 20nm

DFM Implementation flow: 40nm, 28nm

iPDK contents – SPICE, LVS, views, symbols

Tech Files Roadmap – iPDK, iRCS, iDRC, iLVS (65nm to 28nm)

Partners in each area (EDA Vendors)

Analog Base Cell (ABC) – scalaeable analog cells with optimized layout, Pycell and OA symbol, multi-vendor design flow with ABC

Analog/Mixed signal reference flow – goals

AMS Reference Flow 1.0 – used a 1.6GHz PLL

Who
Mehmet Cirit, Founder of Library Technologies

History

I first met Mehmet at Silicon Compilers in the 80’s and have kept in touch with him over the years.

What
New product – Chip Timer, speeds up ASIC designs by building digital library cells on the fly. Uses both Solution Ware and Cell Opt tools to do design optimization. This approach can improve timing by 50%. As an example we took the SPARC processor in 65nm technology and showed how to improve the clock speed from 1.2 GHz to 2.4 GHz.

Q: How is that different than Zenasis?

A: We’re a bit different, they were combining cells, we’re optimizing existing cells per path. We don’t create new cells.

Beta testing right now at an account, stay tuned for a press release.

Yield Opt – Determines best and worst case conditions for each cell to use just two PVT corners. Finds worst and best case timing per cell.  Their tool launches your favorite SPICE circuit simulator to get results and use monte carlo values from the process models. Similar to using exhaustive monte carlo, rather it is using a smart optimization. Anyone with a digital library would benefit from Yield Opt.

Cell Opt – Does timing and power optimization per cell in your library. Tool changes your device sizes to meet your specs on digital cells.

Solution Ware – Creates libraries for logic synthesis tools, also can do libraries for memories and standard cells.

DAC 2010 – It’s a busy year for us and Chip Timer looks to be a revolutionary product.

Customers – Medtronic (biomedical company), Tabula (startup), Exar (mixed-signal).

Our panel discussion on Tuesday afternoon was well attended, thanks to the lively discussion from our three panelists:

Daniel Payne, Aaron Barker, Jin Qin Liu, Pierluigi Daglio

I’ll have to ask the DAC staff if we have a video or audio broadcast of the discussion.

Questions from our audience included:

1. Are you really satisfied with your choice of FastSPICE simulator?
2. How do I fix my simulation when it doesn’t converge?
3. Is anyone using Transient Noise Analysis?