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	<title>EDA Thoughts</title>
	<link>http://www.chipdesignmag.com/payne</link>
	<description>From an EDA marketing insider</description>
	<lastBuildDate>Tue, 24 May 2011 19:55:33 +0000</lastBuildDate>
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	<item>
		<title>3D Extraction &#8211; DAC Panel Session</title>
		<description><![CDATA[
I&#8217;ve organized a pavilion panel session, &#8220;3D Extraction: Coming to a Design Near You?&#8220;. This panel is on Tuesday, June 7 at 3:00PM, booth #3421.
Our moderator is Andrew Kahng (UC San Diego), and panelists: Carey Robertson (Mentor Graphics), Ji Zheng (Apache DA), and Sourav Chakravarty (Intel).
   

]]></description>
		<link>http://www.chipdesignmag.com/payne/2011/05/24/3d-extraction-dac-panel-session/</link>
			</item>
	<item>
		<title>DesignCon 2011</title>
		<description><![CDATA[
I&#8217;ll be attending DesignCon on Monday and Tuesday, intending to visit the following companies to get an update on their EDA tools:

Synopsys &#8211; HSPICE
Cadence &#8211; Spectre, UltraSim, Silicon Realization
Tanner EDA &#8211; PDK
Concept Engineering &#8211; SpiceVision Pro
Altos Design Automation &#8211; Liberate LV
Legend Design &#8211; MSIM
Physware &#8211; PhysApex
Apache DA &#8211; CPM

Monday is a beautiful sunny day here [...]]]></description>
		<link>http://www.chipdesignmag.com/payne/2011/01/30/designcon-2011/</link>
			</item>
	<item>
		<title>Faster IC Designs Without Using a Clock and With Delay Insensitive Results</title>
		<description><![CDATA[Digital designers are taught on day one that they must use synchronous logic design which employ a clock to synchronize all events in their IC design, and so it has been for decades.

Unless of course you have ever designed a DRAM or SRAM memory where self-timed logic is used to squeeze out the ultimate in [...]]]></description>
		<link>http://www.chipdesignmag.com/payne/2010/12/09/faster-ic-designs-without-using-a-clock-and-with-delay-insensitive-results/</link>
			</item>
	<item>
		<title>Thermal Analysis for IC Designs</title>
		<description><![CDATA[Ed Cheng, CEO at Gradient Design Automation recently spoke with me about his unique company focused on thermal analysis of IC designs. I first met Ed at Silicon Compilers in 1986, plus we both worked at Intel before that.
Questions:
Q: Who would use your tools?
A: Our end users are chip designers at the gate and transistor [...]]]></description>
		<link>http://www.chipdesignmag.com/payne/2010/12/02/thermal-analysis-for-ic-designs/</link>
			</item>
	<item>
		<title>EDA and Philanthropy</title>
		<description><![CDATA[In a recession what EDA company would invest in philanthropy?
Actually, many EDA companies have a long-term vision to be philanthropic and encourage a love for science in our younger generation. This month I was invited by Mentor Graphics to attend an event at OMSI, the Oregon Museum of Science and Industry. There is a new [...]]]></description>
		<link>http://www.chipdesignmag.com/payne/2010/11/30/eda-and-philanthropy/</link>
			</item>
	<item>
		<title>EDA without using the Acronym EDA</title>
		<description><![CDATA[Two press releases came out today and they were both from major EDA companies that are now starting to position themselves without using the EDA acronym. Perhaps this is a new but subtle trend to remove the old-fashioned EDA label in favor of something different, new or an expanding scope.
Here is the opening line for [...]]]></description>
		<link>http://www.chipdesignmag.com/payne/2010/11/04/eda-without-using-the-acronym-eda/</link>
			</item>
	<item>
		<title>Semiconductor IP Booms in Q2 2010</title>
		<description><![CDATA[EDAC publishes a quarterly report called the Market Statistics Service and I just read that Semiconductor IP sales jumped 35.3% in Q2 2010 compared to Q2 2009.

The Americas region is still the largest sales territory however APAC grew the most by 41.7%.

Our industry is still in a slump after the peak of 2008:
I&#8217;m a little [...]]]></description>
		<link>http://www.chipdesignmag.com/payne/2010/10/12/semiconductor-ip-booms-in-q2-2010/</link>
			</item>
	<item>
		<title>An HP Laptop with Thermal Issues</title>
		<description><![CDATA[Three years ago I bought an HP Pavilion laptop (DV9000) with a 17inch display running Windows Vista. All has been well until last week when it died. My laptop symptoms were that I pushed the On button and the LED lights turned on for a few seconds, then the computer turned off for a few [...]]]></description>
		<link>http://www.chipdesignmag.com/payne/2010/10/03/an-hp-laptop-with-thermal-issues/</link>
			</item>
	<item>
		<title>Interoperability and EDA Bugs</title>
		<description><![CDATA[I&#8217;ll never forget the shock when I ran some SPICE simulations as a new college graduate working at Intel and my 5V part had a circuit that doubled the VCC supply towards 10V internally to boost the Word Line on a DRAM. The waveforms were plain as day, and the boosted signal didn&#8217;t stop at [...]]]></description>
		<link>http://www.chipdesignmag.com/payne/2010/09/18/interoperability-and-eda-bugs/</link>
			</item>
	<item>
		<title>Ciranova Receives Intel Funding</title>
		<description><![CDATA[At the 2009 DAC I was visiting Ciranova at their booth when an Intel guy walked up and started talking excitedly with an executive about using Ciranova tools, at which point the executive asked me to ignore what was happening in front of my eyes. I honored the request and didn&#8217;t mention it in my [...]]]></description>
		<link>http://www.chipdesignmag.com/payne/2010/09/14/ciranova-receives-intel-funding/</link>
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