<?xml version="1.0" encoding="UTF-8"?>
<rss version="2.0"
	xmlns:content="http://purl.org/rss/1.0/modules/content/"
	xmlns:wfw="http://wellformedweb.org/CommentAPI/"
	xmlns:dc="http://purl.org/dc/elements/1.1/"
	xmlns:atom="http://www.w3.org/2005/Atom"
	xmlns:sy="http://purl.org/rss/1.0/modules/syndication/"
	xmlns:slash="http://purl.org/rss/1.0/modules/slash/"
	>

<channel>
	<title>EDA Thoughts</title>
	<atom:link href="http://www.chipdesignmag.com/payne/feed/" rel="self" type="application/rss+xml" />
	<link>http://www.chipdesignmag.com/payne</link>
	<description>From an EDA marketing insider</description>
	<lastBuildDate>Fri, 05 Feb 2010 15:39:48 +0000</lastBuildDate>
	<generator>http://wordpress.org/?v=2.8.4</generator>
	<language>en</language>
	<sy:updatePeriod>hourly</sy:updatePeriod>
	<sy:updateFrequency>1</sy:updateFrequency>
			<item>
		<title>Carbon Footprint is Good For ICs</title>
		<link>http://www.chipdesignmag.com/payne/2010/02/05/carbon-footprint-is-good-for-ics/</link>
		<comments>http://www.chipdesignmag.com/payne/2010/02/05/carbon-footprint-is-good-for-ics/#comments</comments>
		<pubDate>Fri, 05 Feb 2010 15:39:48 +0000</pubDate>
		<dc:creator>Daniel Payne</dc:creator>
				<category><![CDATA[IC Technology]]></category>
		<category><![CDATA[DARPA]]></category>
		<category><![CDATA[graphene]]></category>
		<category><![CDATA[IBM]]></category>
		<category><![CDATA[SiC]]></category>

		<guid isPermaLink="false">http://www.chipdesignmag.com/payne/?p=374</guid>
		<description><![CDATA[IBM just demonstrated graphene transistors that could become a replacement for pure silicon-based ICs.
&#124;
Photo: Courtesy of IBM, posted at EE Times
The demonstration showed 100GHz operation at room temperature with a production goal of 1THz.
This is funded by DARPA the folks who really created the Internet.
We need to add Silicon-Carbide (SiC) to our vocabulary.
]]></description>
			<content:encoded><![CDATA[<p>IBM just demonstrated graphene transistors that could become a replacement for pure silicon-based ICs.</p>
<p><img class="alignnone" src="http://i.cmpnet.com/eetimes/news/online/2010/02/fastgraphene400.jpg" alt="" width="400" height="487" />|<br />
Photo: Courtesy of IBM, posted at <a href="http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=222601227" target="_blank">EE Times</a></p>
<p>The demonstration showed 100GHz operation at room temperature with a production goal of 1THz.</p>
<p>This is funded by DARPA the folks who really created the Internet.</p>
<p>We need to add Silicon-Carbide (SiC) to our vocabulary.</p>
]]></content:encoded>
			<wfw:commentRss>http://www.chipdesignmag.com/payne/2010/02/05/carbon-footprint-is-good-for-ics/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>So You Want to Start-up an EDA Company?</title>
		<link>http://www.chipdesignmag.com/payne/2010/02/02/so-you-want-to-start-up-an-eda-company/</link>
		<comments>http://www.chipdesignmag.com/payne/2010/02/02/so-you-want-to-start-up-an-eda-company/#comments</comments>
		<pubDate>Wed, 03 Feb 2010 00:08:23 +0000</pubDate>
		<dc:creator>Daniel Payne</dc:creator>
				<category><![CDATA[DVCon]]></category>

		<guid isPermaLink="false">http://www.chipdesignmag.com/payne/?p=371</guid>
		<description><![CDATA[An interactive workshop with angel investor Jim Hogan and start up executive Paul McLellan 
Dire predictions about the death, stagnation or maturation of EDA are premature, says noted angel investor Jim Hogan, a major shaper and influencer of the EDA industry.  He and cohort Paul McLellan actually see lucrative opportunities in EDA.   Startup founders just [...]]]></description>
			<content:encoded><![CDATA[<p><em><a href="http://www.dvcon.com/" target="_blank"><img class="alignleft size-full wp-image-372" style="margin-left: 5px; margin-right: 5px;" title="dvcon2010" src="http://www.chipdesignmag.com/payne/wp-content/uploads/2010/02/dvcon2010.JPG" alt="dvcon2010" width="245" height="122" /></a>An interactive workshop with angel investor Jim Hogan and start up executive Paul McLellan </em></p>
<p>Dire predictions about the death, stagnation or maturation of EDA are premature, says noted angel investor Jim Hogan, a major shaper and influencer of the EDA industry.  He and cohort Paul McLellan actually see lucrative opportunities in EDA.   Startup founders just need to see end-product design trends and find problems to solve that’ll appear in the next 18-24 months.</p>
<p>Come to this workshop and hear how to get a startup going in EDA.     Get Jim and Paul’s take on what areas in EDA and IP are potentially successful – and those areas that won&#8217;t yield a reasonable return on your efforts.</p>
<p>Talk to Jim and Paul about the process of starting up an EDA company – what the angel investment process is, what to expect, how to figure out your exit strategy.</p>
<p><strong>When?</strong></p>
<p>Tuesday</p>
<p>February 23, 2010</p>
<p>6:30 – 7:30 pm</p>
<p>@ DVCon  (<a href="http://dvcon.com/" target="_blank">DVCon </a>registration not required)</p>
<p><strong>Where?</strong></p>
<p>DoubleTree Hotel</p>
<p>Oak Ballroom</p>
<p>2050 Gateway Place</p>
<p>San Jose, CA  95110</p>
<p>1-408-453-4000</p>
<p><strong>RSVP to:</strong></p>
<p><a href="mailto:liz@leepr.com">Liz Massingill</a></p>
]]></content:encoded>
			<wfw:commentRss>http://www.chipdesignmag.com/payne/2010/02/02/so-you-want-to-start-up-an-eda-company/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Mentor Warms up to 3D Field Solvers</title>
		<link>http://www.chipdesignmag.com/payne/2010/01/22/mentor-warms-up-to-3d-field-solvers/</link>
		<comments>http://www.chipdesignmag.com/payne/2010/01/22/mentor-warms-up-to-3d-field-solvers/#comments</comments>
		<pubDate>Fri, 22 Jan 2010 20:07:01 +0000</pubDate>
		<dc:creator>Daniel Payne</dc:creator>
				<category><![CDATA[3D Field Solvers]]></category>
		<category><![CDATA[Extraction tools]]></category>

		<guid isPermaLink="false">http://www.chipdesignmag.com/payne/?p=366</guid>
		<description><![CDATA[When I consulted for the start-up company Physware on their new 3d Field Solver 5 years ago it dawned on me &#8211; IC designers really need the accuracy of 3D Field Solvers to create their frequency-dependent s-parameters for circuit simulation.
Mentor finally acknowledged the same conclusion as Carey Robertson just wrote about this today.
It appears that [...]]]></description>
			<content:encoded><![CDATA[<p><img class="alignleft size-full wp-image-351" title="3d" src="http://www.chipdesignmag.com/payne/wp-content/uploads/2009/12/3d.PNG" alt="3d" width="231" height="191" />When I consulted for the start-up company <a href="http://www.physware.com" target="_blank">Physware</a> on their new 3d Field Solver 5 years ago it dawned on me &#8211; IC designers really need the accuracy of 3D Field Solvers to create their frequency-dependent s-parameters for circuit simulation.</p>
<p>Mentor finally acknowledged the same conclusion as Carey Robertson just <a href="http://chipdesignmag.com/display.php?articleId=3872" target="_blank">wrote about this today</a>.</p>
<p>It appears that Mentor is writing their own 3D field solver instead of just buying one of the many niche tools already on the market.</p>
<p>What I learned from Physware was that the 3D Field Solver market is dominated by companies that have superstar developers with Ph.D. degrees and have been published in technical journals.</p>
<p>All the best to Mentor in their 3D field solver journey.</p>
]]></content:encoded>
			<wfw:commentRss>http://www.chipdesignmag.com/payne/2010/01/22/mentor-warms-up-to-3d-field-solvers/feed/</wfw:commentRss>
		<slash:comments>5</slash:comments>
		</item>
		<item>
		<title>Downward EDA Revenue Trends Continue</title>
		<link>http://www.chipdesignmag.com/payne/2010/01/18/downward-eda-revenue-trends-continue/</link>
		<comments>http://www.chipdesignmag.com/payne/2010/01/18/downward-eda-revenue-trends-continue/#comments</comments>
		<pubDate>Mon, 18 Jan 2010 16:45:38 +0000</pubDate>
		<dc:creator>Daniel Payne</dc:creator>
				<category><![CDATA[Financial]]></category>

		<guid isPermaLink="false">http://www.chipdesignmag.com/payne/?p=364</guid>
		<description><![CDATA[A picture is worth a 1,000 words so take a look at quarterly EDA revenue as compiled by EDAC:

Ron Wilson of EDN has a good summary of Q3 2009 noting that revenue was down 3.3% compared to Q3 2008.
Typical explanations for a decline in EDA revenue include:

Decreasing number of ASIC starts
Increasing number of FPGA starts [...]]]></description>
			<content:encoded><![CDATA[<p>A picture is worth a 1,000 words so take a look at quarterly EDA revenue as compiled by <a href="http://www.edac.org/" target="_blank">EDAC</a>:</p>
<p><img class="alignnone" title="EDA Revenues" src="http://edac.org/mss/2009Q1_MSS.gif" alt="" width="750" height="446" /></p>
<p><a href="http://www.edn.com/article/CA6714964.html" target="_blank">Ron Wilson of EDN</a> has a good summary of Q3 2009 noting that revenue was down 3.3% compared to Q3 2008.</p>
<p>Typical explanations for a decline in EDA revenue include:</p>
<ul>
<li>Decreasing number of ASIC starts</li>
<li>Increasing number of FPGA starts (where tools are free to low-cost)</li>
<li>Tight budgets at IC design firms, making do with old tools</li>
<li>Increased use of IP instead of designing from scratch</li>
<li>Reluctance of IC design companies to use the newest, small geometry nodes, because the older nodes are more cost effective</li>
<li>Lingering global recession</li>
<li>Business models of EDA companies to license &#8220;all you can eat&#8221; deals have diluted the value of tools</li>
</ul>
<p>My personal hope is that device physicists invent a replacement for silicon-based CMOS.</p>
<p>I&#8217;ll never forget the transition from NMOS (which was burning up chips) to CMOS, and I&#8217;d love to see this new generation of nano-technology design continue to eclipse our limited imaginations. This new device technology will certainly require a new generation of EDA tools, then we&#8217;ll see the good-old days return to EDA revenue.</p>
]]></content:encoded>
			<wfw:commentRss>http://www.chipdesignmag.com/payne/2010/01/18/downward-eda-revenue-trends-continue/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>New Parallel SPICE Start-up Company</title>
		<link>http://www.chipdesignmag.com/payne/2009/12/24/new-parallel-spice-start-up-company/</link>
		<comments>http://www.chipdesignmag.com/payne/2009/12/24/new-parallel-spice-start-up-company/#comments</comments>
		<pubDate>Fri, 25 Dec 2009 03:25:03 +0000</pubDate>
		<dc:creator>Daniel Payne</dc:creator>
				<category><![CDATA[Analog Fast SPICE]]></category>
		<category><![CDATA[Fast SPICE]]></category>
		<category><![CDATA[New EDA Tools]]></category>
		<category><![CDATA[SPICE circuit simulation]]></category>
		<category><![CDATA[ADiT]]></category>
		<category><![CDATA[Agilent]]></category>
		<category><![CDATA[Berkeley DA]]></category>
		<category><![CDATA[Cadence]]></category>
		<category><![CDATA[Cybereda]]></category>
		<category><![CDATA[Eldo]]></category>
		<category><![CDATA[FineSim]]></category>
		<category><![CDATA[Gemini]]></category>
		<category><![CDATA[GSim]]></category>
		<category><![CDATA[HSPICE]]></category>
		<category><![CDATA[Infinisim]]></category>
		<category><![CDATA[Magma]]></category>
		<category><![CDATA[Mentor]]></category>
		<category><![CDATA[Nascentric]]></category>
		<category><![CDATA[OmegaSim]]></category>
		<category><![CDATA[PCSIM]]></category>
		<category><![CDATA[RASER]]></category>
		<category><![CDATA[Silvaco]]></category>
		<category><![CDATA[SmartSpice]]></category>
		<category><![CDATA[Spectre APS]]></category>
		<category><![CDATA[Synopsys]]></category>

		<guid isPermaLink="false">http://www.chipdesignmag.com/payne/?p=355</guid>
		<description><![CDATA[SPICE is a wonderful tool for transistor-level circuit designers to predict speed, timing and power of their sensitive designs across Process, Voltage and Temperature regions or corners. One problem is simply run-time of SPICE, it can be slow enough to take days or even weeks to complete a simulation.
Cybereda is the latest start-up EDA company [...]]]></description>
			<content:encoded><![CDATA[<p>SPICE is a wonderful tool for transistor-level circuit designers to predict speed, timing and power of their sensitive designs across Process, Voltage and Temperature regions or corners. One problem is simply run-time of SPICE, it can be slow enough to take days or even weeks to complete a simulation.</p>
<p><a href="http://www.cybereda.com/" target="_blank"><img class="alignleft size-full wp-image-356" style="margin-left: 5px; margin-right: 5px;" title="cybereda" src="http://www.chipdesignmag.com/payne/wp-content/uploads/2009/12/cybereda.PNG" alt="cybereda" width="239" height="83" />Cybereda </a>is the latest start-up EDA company to offer parallel SPICE technology with a tool named <a href="http://www.cybereda.com/?page_id=29" target="_blank">PCSIM</a>. The claims sound reasonable, about a linear speed-up as you add more cores or CPUs to your design.</p>
<p><img class="alignnone" src="http://cybereda.com/wp-content/uploads/2009/12/table_1.PNG" alt="" width="454" height="146" /></p>
<p>An 8-core version of PCSIM leaves commercial SPICE in the dust:</p>
<p><img class="alignnone" src="http://cybereda.com/wp-content/uploads/2009/12/table_21.gif" alt="" width="558" height="140" /></p>
<p>Right now the company web site talks about how great their tool is however we don&#8217;t hear from any customers yet, so stay tuned to learn how this parallel SPICE tool will compete with other earlier entrants, like:</p>
<ul>
<li><a href="http://www.magma-da.com/products-solutions/analysis/finesimspice.aspx" target="_blank">FineSim SPICE</a> (Magma)</li>
<li><a href="http://www.synopsys.com/Tools/Verification/AMSVerification/CircuitSimulation/HSPICE/Pages/WhatNew.aspx" target="_blank">HSPICE multi-thread</a> (Synopsys)</li>
<li><a href="http://www.cadence.com/cadence/newsroom/press_releases/Pages/pr.aspx?xml=121108_aps" target="_blank">Spectre APS</a> (Cadence)</li>
<li><a href="http://www.gemini-da.com/technology_overview.html" target="_blank">GSim </a>(Gemini &#8211; still independent or acquired?)</li>
<li><a href="http://www.gemini-da.com/technology_overview.html" target="_blank">RASER </a>(Infinisim)</li>
<li>Omega Sim (Nascentric &#8211; now defunct, assets purchased by a customer)</li>
<li><a href="http://www.silvaco.com/tech_lib/simulationstandard/1997/oct/a2/a2.html" target="_blank">SmartSpice </a>(Silvaco)</li>
<li><a href="http://www.mentor.com/products/ic_nanometer_design/analog-mixed-signal-verification/eldo/" target="_blank">Eldo </a>(Mentor)</li>
<li><a href="http://www.agilent.com/about/newsroom/presrel/2008/29sep-em08164.html" target="_blank">Agilent </a>(Agilent ADS), <a href="http://www.agilent.com/about/newsroom/presrel/2008/26aug-em08144.html" target="_blank">Agilent </a>(NVIDIA GPUs)</li>
</ul>
<p><a href="http://www.berkeley-da.com" target="_blank">Berkeley DA</a> is hiring a parallel software developer in <a href="http://www.berkeley-da.com/jobs/car/BDA_career_perf_sr.htm" target="_blank">India</a>, so expect another competitor in 2010.</p>
]]></content:encoded>
			<wfw:commentRss>http://www.chipdesignmag.com/payne/2009/12/24/new-parallel-spice-start-up-company/feed/</wfw:commentRss>
		<slash:comments>4</slash:comments>
		</item>
		<item>
		<title>3D Field Solvers can be Fast</title>
		<link>http://www.chipdesignmag.com/payne/2009/12/09/3d-field-solvers-can-be-fast/</link>
		<comments>http://www.chipdesignmag.com/payne/2009/12/09/3d-field-solvers-can-be-fast/#comments</comments>
		<pubDate>Wed, 09 Dec 2009 18:10:37 +0000</pubDate>
		<dc:creator>Daniel Payne</dc:creator>
				<category><![CDATA[3D Field Solvers]]></category>
		<category><![CDATA[Extraction tools]]></category>
		<category><![CDATA[3D field solver]]></category>
		<category><![CDATA[Aptina]]></category>
		<category><![CDATA[Canesta]]></category>
		<category><![CDATA[F3D]]></category>
		<category><![CDATA[QuickCap]]></category>
		<category><![CDATA[R3D]]></category>
		<category><![CDATA[Raphael]]></category>
		<category><![CDATA[Silicon Frontline]]></category>

		<guid isPermaLink="false">http://www.chipdesignmag.com/payne/?p=347</guid>
		<description><![CDATA[In SoC designs today parasitic extraction tools produce RC and sometimes L or S-parameter values for full-chip designs using either pattern-matching or equation-based techniques. It gets the job done for most digital designs however when you really need accuracy in your parasitics then you must consider something more accurate, namely a 3D field solver.
 
Most [...]]]></description>
			<content:encoded><![CDATA[<p>In SoC designs today parasitic extraction tools produce RC and sometimes L or S-parameter values for full-chip designs using either pattern-matching or equation-based techniques. It gets the job done for most digital designs however when you really need accuracy in your parasitics then you must consider something more accurate, namely a 3D field solver.</p>
<p><img class="alignnone size-full wp-image-351" title="3d" src="http://www.chipdesignmag.com/payne/wp-content/uploads/2009/12/3d.PNG" alt="3d" width="231" height="191" /> <img class="alignnone size-full wp-image-352" title="ic layout" src="http://www.chipdesignmag.com/payne/wp-content/uploads/2009/12/ic-layout.PNG" alt="ic layout" width="185" height="192" /></p>
<p>Most 3D field solvers are slow (compared to pattern-matching) and quickly consume RAM which then limits the practical capacity to cells or small blocks.</p>
<p><a href="http://siliconfrontline.com/" target="_blank"><img class="alignnone size-full wp-image-348" title="silicon frontline" src="http://www.chipdesignmag.com/payne/wp-content/uploads/2009/12/silicon-frontline.PNG" alt="silicon frontline" width="233" height="80" /></a></p>
<p><a href="http://siliconfrontline.com/" target="_blank">Silicon Frontline</a> saw this opportunity and announced products <a href="http://www.chipdesignmag.com/payne/2009/08/14/silicon_frontline/" target="_self">earlier this year</a> to address 3D extraction (F3D) and 3D resistance for power devices (R3D). I spoke today with Dermott Lynch of Silicon Frontline to get an update since August 2009.</p>
<p><a href="http://canesta.com/products-and-technology/products/canestavision-chips" target="_blank"><img class="alignnone size-full wp-image-349" title="canesta" src="http://www.chipdesignmag.com/payne/wp-content/uploads/2009/12/canesta.PNG" alt="canesta" width="164" height="53" /></a></p>
<p><a href="http://canesta.com/products-and-technology/products/canestavision-chips" target="_blank">Canesta </a>sees value in using F3D for their line of 3D image sensors. It saves them time from having to build a test chip and make measurements, now they can simulate with confidence.</p>
<p><a href="http://www.aptina.com/products/image_sensors/" target="_blank"><img class="alignnone size-full wp-image-350" title="aptina" src="http://www.chipdesignmag.com/payne/wp-content/uploads/2009/12/aptina.PNG" alt="aptina" width="188" height="65" /></a><br />
<a href="http://www.aptina.com/products/image_sensors/" target="_blank">Aptina </a>is a second image sensor design company using the F3D tool to shave <a href="http://siliconfrontline.com/PR_Silicon_FrontLine_Image_Sensor_Customer111909.pdf" target="_blank">4 months off</a> their product schedules using simulation with accurate parasitics.</p>
<p>Designs requiring this high accuracy include: SRAM, DRAM, Flash, image sensors, ADC.</p>
<p>In evaluations there is always the question of a reference for accuracy comparisons so the venerable <a href="http://www.magma-da.com/products-solutions/libraryCharacterization/quickcap.aspx" target="_blank">QuickCap </a>and <a href="http://www.synopsys.com/Tools/TCAD/CapsuleModule/raphael_ds.pdf" target="_blank">Raphael </a>tools are often used. F3D compares well with these reference tools then really shines when you turn on the manufacturing effects.</p>
<p>In 2010 you can expect to see:</p>
<ul>
<li>Endorsements from foundries</li>
<li> Speed improvements</li>
<li>Two new products</li>
</ul>
<p>This EDA company has found a niche in offering fast and accurate 3D extraction and a growing list of customers.</p>
]]></content:encoded>
			<wfw:commentRss>http://www.chipdesignmag.com/payne/2009/12/09/3d-field-solvers-can-be-fast/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Power Consumption, Smartphones and EDA</title>
		<link>http://www.chipdesignmag.com/payne/2009/11/28/power-consumption-smartphones-and-eda/</link>
		<comments>http://www.chipdesignmag.com/payne/2009/11/28/power-consumption-smartphones-and-eda/#comments</comments>
		<pubDate>Sat, 28 Nov 2009 17:36:09 +0000</pubDate>
		<dc:creator>Daniel Payne</dc:creator>
				<category><![CDATA[Power and Noise Integrity]]></category>
		<category><![CDATA[Android]]></category>
		<category><![CDATA[Apple]]></category>
		<category><![CDATA[Droid]]></category>
		<category><![CDATA[iPhone]]></category>
		<category><![CDATA[Motorola]]></category>
		<category><![CDATA[Verizon]]></category>

		<guid isPermaLink="false">http://www.chipdesignmag.com/payne/?p=344</guid>
		<description><![CDATA[I&#8217;ve been tempted to upgrade to a Smartphone like the iPhone 3GS or Droid because of the rich set of features and I want to appear hip.

Doing some research on each of these phones reveals a common weakness &#8211; short battery life. The Droid or iPhone battery can last a mere 4 hours with just [...]]]></description>
			<content:encoded><![CDATA[<p>I&#8217;ve been tempted to upgrade to a Smartphone like the iPhone 3GS or Droid because of the rich set of features and I want to appear hip.</p>
<p><img class="alignnone" src="http://images.pcworld.com/news/graphics/181554-verizon-droid-reviews_original.jpg" alt="" width="68" height="127" /><img class="alignnone" src="http://images.apple.com/batteries/images/batteriesiphone20090617.jpg" alt="" width="247" height="110" /></p>
<p>Doing some research on each of these phones reveals a common weakness &#8211; short battery life. The <a href="http://www.pcworld.com/businesscenter/article/181684/droid_battery_life_requires_new_charging_habits.html" target="_blank">Droid</a> or <a href="http://www.latimes.com/business/la-fi-iphone3-2009jul03,0,2546606.story" target="_blank">iPhone </a>battery can last a mere 4 hours with just a few emails, phone calls and minutes of web surfing.</p>
<p>Being a real enthusiast for efficiency I&#8217;ve decided to pass on getting one of these phones for right now however the question remains &#8211; why is the battery life so short?</p>
<p>It could be just a case of the marketing department adding too many features that all consume power:</p>
<ul>
<li>Huge screens</li>
<li>WiFi</li>
<li>Navigation</li>
<li>Music</li>
<li>Video</li>
<li>Email</li>
<li>Web browsing</li>
<li>Bluetooth</li>
</ul>
<p>Some people think that the power issue will be resolved with the next release of the operating system, so that it auto detects how you are using the Smartphone and aggressively manages power to keep the device running for the maximum time.</p>
<p>I&#8217;m wondering if these phone companies did any high-level simulations of power consumption?</p>
<p>Are there EDA simulators that would predict power consumption on a complete consumer electronic device like the Droid or iPhone?</p>
<p>Did the marketing departments ignore the battery life issue?</p>
<p>How will engineering produce a longer living Smartphone?</p>
<p>EDA could add some real value here in helping the system-level designers of Smartphones to get extended life out of a single battery charge.</p>
<p>Even the foundries could add some value by offering a process with lower leakage currents, and lower switching power.</p>
]]></content:encoded>
			<wfw:commentRss>http://www.chipdesignmag.com/payne/2009/11/28/power-consumption-smartphones-and-eda/feed/</wfw:commentRss>
		<slash:comments>6</slash:comments>
		</item>
		<item>
		<title>Windows Vista and the Falcon Framework</title>
		<link>http://www.chipdesignmag.com/payne/2009/11/17/windows-vista-and-the-falcon-framework/</link>
		<comments>http://www.chipdesignmag.com/payne/2009/11/17/windows-vista-and-the-falcon-framework/#comments</comments>
		<pubDate>Tue, 17 Nov 2009 17:30:40 +0000</pubDate>
		<dc:creator>Daniel Payne</dc:creator>
				<category><![CDATA[Extraction tools]]></category>
		<category><![CDATA[Financial]]></category>
		<category><![CDATA[IC Layout Editors]]></category>
		<category><![CDATA[Mixed signal simulation]]></category>
		<category><![CDATA[SPICE circuit simulation]]></category>
		<category><![CDATA[Web marketing]]></category>
		<category><![CDATA[ADiT]]></category>
		<category><![CDATA[BSIM]]></category>
		<category><![CDATA[Calibre]]></category>
		<category><![CDATA[Eldo]]></category>
		<category><![CDATA[IC Station]]></category>
		<category><![CDATA[Mentor Graphics]]></category>
		<category><![CDATA[Microsoft]]></category>
		<category><![CDATA[Open Access]]></category>
		<category><![CDATA[Windows 7]]></category>
		<category><![CDATA[Windows Vista]]></category>

		<guid isPermaLink="false">http://www.chipdesignmag.com/payne/?p=341</guid>
		<description><![CDATA[I just upgraded my laptop from Windows Vista to Windows 7 and it got me thinking about Mentor&#8217;s Falcon Framework. How are the two even related?
When Microsoft introduced Vista they assumed that the installed base of XP users would be excited to try something new and better. Well, history showed something like only 25% of [...]]]></description>
			<content:encoded><![CDATA[<p><img class="alignleft" src="http://blogs.ft.com/techblog/files/2009/10/windows7.jpg" alt="" width="140" height="140" />I just upgraded my laptop from Windows Vista to Windows 7 and it got me thinking about Mentor&#8217;s <a href="http://en.wikipedia.org/wiki/Falcon_Framework" target="_blank">Falcon Framework</a>. How are the two even related?</p>
<p>When Microsoft introduced Vista they assumed that the installed base of XP users would be excited to try something new and better. Well, history showed something like only 25% of the installed XP based dared to even try Vista after all of the horror stories about driver incompatibilities, bugs, increased memory usage, slow response, and lack of compelling new features.</p>
<p>When Microsoft figured out that Vista bombed in the marketplace they wisely renamed the successor Windows 7, no mention of that failed &#8220;Vista&#8221; to be ever spoken of again.</p>
<p>From a technology perspective Windows 7 will look and feel totally familiar to any Vista user. In fact, most all of your Vista drivers and applications will simply work in Windows 7. Marketing named this &#8220;Windows 7&#8243; when it feels like Vista that starts a bit faster, and closes quicker. Oh, yes, they did add more eye candy, and some new features. In the next one year of use I will not be more productive than the time it took me to install Windows 7.</p>
<p>Let&#8217;s get back to EDA now and talk about <a href="http://www.mentor.com/" target="_blank">Mentor Graphics</a> and the Falcon Framework. This unified framework was supposed to make all of my EDA point tools look and feel the same, use the same database, and just make me more productive. History showed that the release of 8.0 was 2 years late and failed to deliver on it&#8217;s promises, so Mentor was knocked down in the revenue rankings.</p>
<p><img class="alignnone size-full wp-image-342" title="falcon framework" src="http://www.chipdesignmag.com/payne/wp-content/uploads/2009/11/falcon-framework.PNG" alt="falcon framework" width="583" height="443" /></p>
<p>Today at Mentor the word &#8220;Falcon&#8221; is not uttered, just like &#8220;Vista&#8221; is not talked about at Microsoft.</p>
<p>Mentor learned its lesson and now works with industry standards groups and adds value by being compatible and working in EDA flows. Examples include:</p>
<ul>
<li>OpenAccess and OASIS for Calibre</li>
<li>BSIM3/4 models and HSPICE netlists for Eldo and ADiT</li>
<li>VHDL/Verilog standards for ModelSim</li>
<li>SPIRIT Consortium, OSCI</li>
<li>etc</li>
</ul>
<p>A handful of Mentor tools still use the Falcon Framework technology (Design Architect, IC Station, &#8230;) however all new tools in the last decade avoid it.</p>
<p>Now if Microsoft could just build a web browser that conformed to <a href="http://www.w3c.org" target="_blank">W3C </a>standards, or if W3C would at least have the power to enforce the standards that are written&#8230;.</p>
]]></content:encoded>
			<wfw:commentRss>http://www.chipdesignmag.com/payne/2009/11/17/windows-vista-and-the-falcon-framework/feed/</wfw:commentRss>
		<slash:comments>4</slash:comments>
		</item>
		<item>
		<title>EDA Poster Child for Success</title>
		<link>http://www.chipdesignmag.com/payne/2009/11/03/eda-poster-child-for-success/</link>
		<comments>http://www.chipdesignmag.com/payne/2009/11/03/eda-poster-child-for-success/#comments</comments>
		<pubDate>Tue, 03 Nov 2009 19:14:29 +0000</pubDate>
		<dc:creator>Daniel Payne</dc:creator>
				<category><![CDATA[Financial]]></category>
		<category><![CDATA[Mergers and Acquisitions]]></category>
		<category><![CDATA[Power and Noise Integrity]]></category>
		<category><![CDATA[Apache]]></category>
		<category><![CDATA[Springsoft]]></category>

		<guid isPermaLink="false">http://www.chipdesignmag.com/payne/?p=339</guid>
		<description><![CDATA[I&#8217;ve written before (1,2,3,4) about the success and momentum of Apache Design so it was no surprise to read in EE Times that they are positioning for an IPO.
Every quarter for the past several years I would read almost the same press release from Apache, &#8220;record sales, still profitable&#8221;. Apache is my favorite EDA poster [...]]]></description>
			<content:encoded><![CDATA[<p><a href="http://www.apach-da.com/"><img class="alignleft" src="http://apache-da.com/apache-da/data/apache-logo.gif" alt="" width="148" height="75" /></a>I&#8217;ve written before (<a href="http://www.chipdesignmag.com/payne/2009/09/08/apache-acquires-sequence/" target="_self">1</a>,<a href="http://www.chipdesignmag.com/payne/2009/07/29/apache-design-automation/">2</a>,<a href="http://www.chipdesignmag.com/payne/2009/07/26/sunday-at-dac/">3</a>,<a href="http://www.chipdesignmag.com/payne/dac-2008-trip-report/">4</a>) about the success and momentum of Apache Design so it was no surprise to read in <a href="http://www.eetimes.com/showArticle.jhtml?articleID=221600023" target="_blank">EE Times</a> that they are positioning for an IPO.</p>
<p>Every quarter for the past several years I would read almost the same press release from Apache, &#8220;record sales, still profitable&#8221;. Apache is my favorite EDA poster child for success.</p>
<p>They&#8217;ve worked hard to carve out a niche for themselves in the EDA space. I think that they could add a few more point-tool companies and expand their product offerings even wider.</p>
<p>I&#8217;d love to see Apache merge with a company like <a href="http://www.springsoft.com/" target="_blank">SpringSoft </a>because there is no product overlap and it could be good for the industry. Time will tell.</p>
]]></content:encoded>
			<wfw:commentRss>http://www.chipdesignmag.com/payne/2009/11/03/eda-poster-child-for-success/feed/</wfw:commentRss>
		<slash:comments>2</slash:comments>
		</item>
		<item>
		<title>Telesales works in EDA</title>
		<link>http://www.chipdesignmag.com/payne/2009/10/14/telesales-works-in-eda/</link>
		<comments>http://www.chipdesignmag.com/payne/2009/10/14/telesales-works-in-eda/#comments</comments>
		<pubDate>Wed, 14 Oct 2009 14:00:56 +0000</pubDate>
		<dc:creator>Daniel Payne</dc:creator>
				<category><![CDATA[FPGA Tools]]></category>
		<category><![CDATA[Financial]]></category>
		<category><![CDATA[PCB]]></category>
		<category><![CDATA[Aldec]]></category>
		<category><![CDATA[Altium]]></category>
		<category><![CDATA[EMA]]></category>

		<guid isPermaLink="false">http://www.chipdesignmag.com/payne/?p=334</guid>
		<description><![CDATA[EMA has been selling the OrCAD product line to PCB designers for several years now so it makes sense as they broaden their product lines to add the Aldec tools.
My only question about this kind of distribution agreement is what happens to channel conflict between Aldec&#8217;s existing sales channel and the new EMA channel.
Telesales is [...]]]></description>
			<content:encoded><![CDATA[<p><a href="http://www.ema-eda.com" target="_blank"><img class="alignleft size-full wp-image-335" title="ema" src="http://www.chipdesignmag.com/payne/wp-content/uploads/2009/10/ema.gif" alt="ema" width="211" height="39" />EMA </a>has been selling the OrCAD product line to PCB designers for several years now so it makes sense as they <a href="http://www.ema-eda.com/documents/PR_Aldec_Active-HDL.pdf" target="_blank">broaden their product lines</a> to add the <a href="http://www.aldec.com/" target="_blank">Aldec </a>tools.</p>
<p><img class="alignleft size-full wp-image-336" title="aldec" src="http://www.chipdesignmag.com/payne/wp-content/uploads/2009/10/aldec.JPG" alt="aldec" width="150" height="138" />My only question about this kind of distribution agreement is what happens to channel conflict between Aldec&#8217;s existing sales channel and the new EMA channel.</p>
<p>Telesales is alive and well in EDA for tools priced under $30K per seat. OrCAD was a pioneer in making telesales work in the PCB side of EDA.</p>
<p><a href="http://www.altium.com/">Altium </a>is another EDA competitor to Aldec in this segment that uses resellers.</p>
]]></content:encoded>
			<wfw:commentRss>http://www.chipdesignmag.com/payne/2009/10/14/telesales-works-in-eda/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
	</channel>
</rss>
