ACCIT – Parallel SPICE, http://www.accit-newsystemsresearch.com/

Altos DA – Cell characterization, http://www.altos-da.com/

Analog Rails - schematic driven layout, http://www.analograils.com/

*AnSyn – analog optimization, http://www.ansyn.com/

Apache DA – power, noise, reliability, http://www.apache-da.com/

*ATEEDA – analog test, http://www.ateeda.com/

Berkeley DA – Analog FastSPICE, http://www.berkeley-da.com

Cadence – AMS verification, http://www.cadence.com

CiraNova – Analog Layout Automation, http://www.ciranova.com/

Magma - FastSPICE, www.magma-da.com

Mentor – Questa ADMS, ADiT, http://www.mentor.com

*Mephisto DA – analog optimization, http://www.mephisto-da.com

Micro Magic – full custom IC layout, www.micromagic.com

*SkillCAD – accelerating custom IC layout, www.skillcad.com

Solido DA – analog design improvement, www.solidodesign.com

Springsoft – Laker, custom IC layout, www.springsoft.com

Synopsys – Custom SIM, Custom Designer, http://www.synopsys.com

Tela Innovations – 1D layout, www.tela-inc.com

Companies marked with an * are first-time DAC exhibitors. I’ll also be attending:

Monday - Mentor and ARM, lunch and learn
Tuesday - Synopsys AMS Verification breakfast

Tuesday - IPL luncheons

Tuesday - Denali party

Let me know if I’m missing any interesting transistor-level EDA companies.

As we head toward this year’s DAC, now in its 46th consecutive year, starting July 27, let’s look forward and not back to see what’s new and exciting, and what you can expect this year.

We’ll be treated to four keynote sessions, including a special Monday Keynote Panel, “Futures for EDA: The CEO View,” with three EDA CEOs, and a special plenary panel Thursday titled, “How Green Is My Silicon Valley.”

The technical program has 54 research paper sessions covering approximately 13 topics and featuring 156 talks selected from 733 submissions worldwide, a 10 percent increase over the number received last year.  A new highlight of the technical program that we’re all quite proud of is the three-day User Track, with more than 40 presentations and 42 posters focused on the latest in tool use and methodologies.  Each submission was reviewed by a 20-member industry user committee.  Additionally, DAC will host nine special sessions and six full-day tutorials that will be held Monday and Friday.

Eight panels are included in the conference’s technical program, while 19 are scheduled for the DAC Pavilion on the exhibit floor.

If that’s not enough, 11 events will be collocated with DAC and there are countless number of sessions at the IC Design Central Partner Pavilion, the Exhibitor Forum and additional meetings hosted by the community.

Many volunteers work together to plan DAC.  DAC’s Executive Committee is made up of 16 members of the EDA and design community who plan the conference, and 15 people work on the Panel Committee.  Organizer MP Associates has 14 employees working year-round on DAC.  The number of members of the Technical Program Committee is 76, while the number of reviewers is staggering: 538.  And, the Exhibitor Liaison Committee of 17 representatives from exhibit companies offers advice on exhibitor-related issues.
And speaking of exhibits, where else but DAC can you find the entire ecosystem of design?  The exhibit hall will be filled with more than 200 vendors of all sizes, including industry leaders Cadence, Magma, Mentor and Synopsys.

As we’ve surely proven, DAC is not to be missed this year.  Register today and be prepared for an information-packed week.  We look forward to seeing you in San Francisco.
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Note:  This year’s DAC will be held July 26-31 at the Moscone Center in San Francisco.  Register today at:  www.dac.com.

I’ll have a chance to speak with either Chi-Ping Hsu, Senior Vice President of Research and Development for the Implementation Products Group or Nimish Modi, Senior Vice President of Research and Development for the Front End Group.

I’m rather curious about the mindset of buy versus build in their roadmap. When Fister took over Cadence it sounded like they only wanted internal development. Now they can reset expectations and set a new course.

Let me know what kind of questions you would like to ask of Cadence R&D and I’ll bring it up during our briefing.

Today I had a briefing with Vishal Kapoor at Cadence to learn more about their SaaS story. Over the past 8 years the services group at Cadence has been working closely with EDA clients to help them better manage tools, flows and methologies in a secure way using networking. In September 2008 we learned that Cadence was offering SaaS. In May I wrote about SaaS and using Xuropa to evaluate new EDA tools.

When I first started thinking about SaaS for EDA the kind of tools that came to mind were batch-oriented for tasks like: DRC, OPC, LVS, P&R, logic synthesis, Logic verification, ATPG, regression testing, etc. However now that we have higher speed networking connections it is even becoming possible to perform interactive tasks like IC Layout and waveform viewing.

You’ll get the biggest cost savings by choosing an all-Cadence tool flow, although the services group will certainly integrate any tool that you’d like. You also get to decide the version of software that you want to design with.

Small IC design groups that don’t have any existing tools will quickly benefit from this SaaS approach although I can see that even the medium and global design teams should also consider outsourcing their design environment. Imagine signing a contract and being able to start your design team working in a day or so with tools that work together in proven IC design flow, without having to invest in your own IT and CAD groups.

My concerns about security, uptime and flexibility were all addressed by the SaaS offering at Cadence. I see this as a real innovation in how IC design can be done in the future, so my next question is, “When will Mentor, Synopsys and Magma follow the leadership of Cadence?”

I recall rules at the exhibit area where they had a cut-off time on Sunday nights and if you left your exhibit after the designated time then you couldn’t return to your booth. It was commonplace for vendors to spend the entire night getting their machines and demos up and running.

Our corporate goal was simple - attract clients and prospects into our demo suites all day so that they wouldn’t have any time to see competitor tools in the other suites. We actually ran the software tools on real or demo designs to show off the features, plus a little time with overhead slides to show off the product roadmap. Fancy presentations were shown with 35mm color slides.

Eventually the DAC structure changed so that the demo suites were no longer off-site, they were integrated into the same exhibit area as the booths. Still, in the 90’s we could witness live product demos up and down the aisles of booths. You could easily spot the buzz at DAC by how deep the crowds were around the live demos.

Eventually we saw the demise of live demos in the booths instead replaced by theatre presentations with slick MTV-style movie clips. You had to be invited into the suites to see live demos running.

One year IBM decided to make a huge splash at DAC to showcase their internal tools to the world. They were very impressive and the people showing the demos were either tool developers or IC designers, and very knowledgable. I recall getting into one of their demo suites only to be escorted out of the suite during the presentation, “for competitive” reasons.

In recent years I’ve notice that even in the suites we are seeing mostly PowerPoint slides and screen shots with fewer and fewer live demos of tools. The thinking must be that CAD managers only want the big picture while actual tool users are not attending DAC as much due to shrinking travel budgets. CAD managers want to lower the risk of buying and using a new tool, so stability is most important.

The last year that Cadence attended the DAC exhibit area they trimmed down the number of tools being shown. I couldn’t even find one person to talk about their FastSPICE tool. Cadence was the first large and public EDA company to pull out of the exhibit area in favor of promoting their own tradeshow. I can understand the thought process to have their own show and keep the attention of their clients loyal to the Cadence brand.

Free Monday at the exhibit area has been around for many years and created a flood of interested people on opening day. This year there is no free Monday, so I expect exhibit traffic to be much lower than in past years. It looks like a blunder by the DAC committee to limit exhibit attendance by charging $50.

Cadence use to throw the biggest DAC party, however now it’s the Denali party that you do not want to miss.

Let’s see what new trends emerge at DAC 2009 in San Francisco.

Excellent Gains

What an amazing gain we’ve seen in EDA stock prices in just the past 3 months. Magma (LAVA) doubling in price, then Mentor (MENT) increasing some 50%.

Ironically Synopsys (SNPS) has been reporting the healthiest quarterly reports yet it’s stock price has been steady and under-performing even the NASDAQ average. I expected Synopsys stock to be boosted by reports of quarterly profits and a growing market share.

You could attribute the Magma stock movements as an indicator that it is ready to be acquired.

Mentor is likely to become the new #2 company in EDA revenue this year, surpassing Cadence. It makes sense that Mentor stock is growing faster than Cadence.

Cadence stock is climbing as the company down-sizes and re-focuses under new leadership. Wall street loves to see management taking action to correct past mistakes. Does anybody know what Michael Fister is doing these days?

Do I expect to see EDA stock prices double again in the next 3 months? No, I’m expecting downward corrections to all stocks as we watch Chrysler go bankrupt or get acquired.

I first became aware of this yesterday when I received an email from Cadence about their Verification IP. Being curious I requested access and was approved within an hour or so by Tom Hackett, an administrator of Cadence VIP. Login was straight forward and there was even a tutorial on how to use their lab examples.

In the old days if you were interested in an EDA tool you had to phone or email your EDA account manager (i.e. sales guy), answer some qualifying questions, ask for an evaluation, install the software, learn the tutorials, then start to run your own designs. This could take weeks to months of time and effort.

With Xuropa we now have the ability in EDA to start evaluating tools within an hour or so without installing software and talking to an Account Manager.

Cadence is dabbling with this technology and only has very limited products for you to evaluate in this manner. This could be a really good thing for both the EDA vendor and tool users.

by David Stannard
I think that this is a smart move for Mentor. It further consolidates the strength of their offerings and is a natural continuation of their 2008 NXP (Philips) test technology and customer acquisition.

Mentor’s deterministic (ATPG and compressed ATPG offerings) are the best in the industry. Their logic and memory BIST are very good. Their diagnostics and yield management is very strong and probably the predominant solution used by the semiconductor industry. And they have the key strategic relationships with universities, industry thought leaders and other suppliers to the manufacturing test/yield supply chain.

Logic Vision brings some interesting value from the diagnostics space, some remaining BIST capabilities to round out the already strong Mentor and Mentor/NXP in house solution. LV was selling some of Mentor’s tools (Fastscan) and has provided a strong infrastructure for the at speed clock generation.

Synopsys and Cadence have both abandoned Logic BIST long time back leaving that territory to Mentor and LV.

Additionally, LV was working and has experience in the analog testing space. So it is an excellent blocking move against Cadence (one of their traditional strengths used to be be analog / mixed signal design) moving into analog / mixed signal test.

Mentor like Synopsys have invested into a very knowledgeable AE force, making the products easy to sell by their sales force and have provided all the key elements of the whole solution. Well architected documentation, training, customer support and packaging/pricing. There are a lot of well educated Mentor tool alumni that can be brought into a company and ramp to maximum productivity in the shortest time.

And finally, Mentor’s DFM, layout verification and manufacturing yield improvement leveraging test was already strong prior to acquiring the NXP technology and customers. Mentor has given much more thought and effort into the architecture of a whole product solution. Cadence appears to have largely capitulated from DFM in the Novemeber 2008 RIFF’s while Synopsys has a strong offering. LV provides additional customers to Mentor and the LV install base must just be loving the opportunity to deal with a financially sound, proven long term leader like Synopsys.

As to the Cadence question: in general, Cadence’s solutions have not kept pace at the rate that industry needs. So a consolidation of industry players seems obvious and IMO, Cadence has the weakest position and the most to lose. Synopsys still shows a higher degree of hunger to be a major test player.

So, I feel that this is a win for Mentor, a win for the old LV customers, and increased pressure for Synopsys and Cadence. IMO, Mentor is #1, consolidates its ability to be #1 for existing customers and with the majority of the remaining market being held by Synopsys.

You don’t get fired for purchasing Design Compiler or Prime Time and I believe that you won’t get fired for buying Mentor’s even stronger test tools.

My expectation was that I could simply download the software and start evaluating it however it was more complex than that. I filled out a request form then received a pleasant phone call from a Tanner person that qualified me. Several days later I received a package in the mail with my software and dongle.

Installation worked as documented and I started working through the tutorials. I didn’t like the idea of a hardware dongle and prefer the FlexLM license instead. I remember in the early days that Viewlogic used hardware dongles as well. I can understand how dongles cut down on illegal copies.

Schematic capture (S-Edit) and custom IC layout tools (L-Edit) from Tanner have been around for some 20 years now, so I didn’t find any glaring bugs to report. The user interface was familiar to anyone with Windows experience. I could even change color schemes to make it look more like Mentor or Cadence tools.

SPICE simulation (T-Spice) is well integrated with schematics and viewing. I’d love to see a FastSPICE tool or support for multi-core to speed up my circuit simulations.

Tanner folks phoned me to answer questions about features, comparisons and product roadmap.

The ideal user for Tanner tools is someone working on smaller custom IC or MEMs designs. Areas for improvement would be support of multi-user, team-based design with check-in and check-out capabilities. Cadence users would be attracted to a Tanner version that used OpenAccess.

Calibre and Dracula users can import rule decks for LVS and DRC runs (HiPer Verify).

From a marketing view there’s been another welcome change in recent press releases from Tanner, they are now quoting customers and showing how customers are being successful. Previous press releases focused soley and technical features and not customer benefits.

Tanner EDA appears to be a very solid, yet conservative kind of EDA provider that has found a niche by offering custom IC tools to budget-conscious users that often integrate with Cadence and Mentor tools.

Agilent - EM simulation using NVIDIA
Mentor - RET using Cell BE
Nascentric - FastSPICE using NVIDIA
Gauda - OPC using NVIDIA

The typical barrier to adopting GPUs is simple, you have to re-write your code. Many EDA companies do not want to re-write code because it is too costly in terms of time or perhaps the original software architect has moved on to another project or company and isn’t available to explore the benefits.

The technology competitor to GPUs is to simply stick with AMD and Intel CPUs on their quest to add more cores. This approach still requires a software re-write to keep each core busy.

I was impressed to learn last week that Synopsys is now offering multicore support in their FastSPICE simulators under the new product name CustomSim (NanoSim, HSIM, XA). Users don’t have to pay any extra upgrade fee to get the benefit of speed improvements using multicore workstations. Other EDA vendors are charging extra for multicore support.

Perhaps start-ups will lead the way in using GPUs and multicore to maximum benefit, then get acquired by the established EDA vendors.