I’ve organized a pavilion panel session, “3D Extraction: Coming to a Design Near You?“. This panel is on Tuesday, June 7 at 3:00PM, booth #3421.

Our moderator is Andrew Kahng (UC San Diego), and panelists: Carey Robertson (Mentor Graphics), Ji Zheng (Apache DA), and Sourav Chakravarty (Intel).

I’ll be attending DesignCon on Monday and Tuesday, intending to visit the following companies to get an update on their EDA tools:

• Synopsys – HSPICE
• Cadence – Spectre, UltraSim, Silicon Realization
• Tanner EDA – PDK
• Concept Engineering – SpiceVision Pro
• Altos Design Automation – Liberate LV
• Legend Design – MSIM
• Physware – PhysApex
• Apache DA – CPM

Monday is a beautiful sunny day here in Santa Clara:

Unless of course you have ever designed a DRAM or SRAM memory where self-timed logic is used to squeeze out the ultimate in performance. I started out designing DRAM circuits at Intel (when they were still in the DRAM business) and was delighted to learn that my chip was using self-timed logic to increase performance and simplify the interface requirements when the memory was placed on a board.

Self-timed logic for Memory, Patent 6785184 (Intel)

What would happen if you could design your digital logic without the use of clocks?

Indeed, you could benefit by:

1. Faster operation
2. Process variation tolerance, delay insenstive
3. Lower power (no clocks)
4. Low current peaks
5. Operate over a wider voltage range
6. Lower latency
7. Quicker wake-up times

Steve Svoboda

I recently met with Steve Svoboda from Tiempo IC, a company offering IP and EDA tools for clockless design.

Q: What is your history in EDA?

A: I worked at Alta which was bought by Cadence in 1995 and was the product line manager for SPW. I used Alta at GTE then joined Alta. Cadence also bought Redwood Design Automation and the product lines merged and were called the Alta Group.

Q: What is the mission of Tiempo IC?

A: To raise the abstraction of self-timed IC design from the transistor level to the RTL.

Q: Who founded the company?

A: Marc Renaudin, former Professor at Grenoble INP did research in asyncrhonous logic as applied to crypto processor design along with logic synthesis.

Q: How does asynchronous logic work?

A: In between logic stages there’s an asynchronous register (Muller Gate, C-Element), then combine that with dual-rail encoding of data (provide delay insensitive design). An acknowledgment is sent back that data was received, then it’s ready to send the next data.

C-element, Muller gate

Four-phase communication protocol

Dual Rail Encoding

Q: How does the asynchronous approach differ from synchronous logic?

A: In synchronous logic your design is limited by the slowest path, and this design style creates current spikes at each edge of the clock.

Q: With synchronous logic I have a well-founded test plan. How do I test a clockless design?

A: Asynchronous is not testable in the same way that synchronous design is. On the plus side we don’t have race conditions or glitches to contend with. Our testability problem is really combinational logic instead of sequential logic, which means a huge reduction in the number of logic states.

Q: Is there any ATPG with asynchronous logic?

A: Stay tuned for more info.

Q: How testable would a CPU be in clockless design?

A: We built and tested a 16 bit CPU which required only 420 vectors to test, compared to traditional sequential designs which would require thousands of vectors to test.

Q: What is the input language for your EDA design flow?

A: Our tool accepts SystemVerilog.

Q: Who else has designed clockless chips?

A: Handshake Solutions did an ARM core for Philips that was clockless.

A: Achronix is an FPGA company with asynchronous design and their parts run at 1.5GHz rates.

A. Fulcrum Microsystems offer switches that are asynchronous providing the lowest latency in the market plus lower power.

Q: What are the big benefits of using clockless design?

A: Lower power and delay insensitive designs.

Q: What does Tiempo IC offer today?

A: Both IP cores and EDA tools for asynchronous designs.

Q: Can you mention any customer names yet?

A: No, we are under NDA and the customers are not allowing us to talk about them yet.

Q: Can I run a Static Timing Analysis (STA) tool on your asynch designs?

A: Yes, any commercial STA tool will work on our designs.

Q:  For your synthesis tool, what is the capacity?

A:  We have not yet tried to measure the capacity of ACC.  But we routinely synthesize blocks of around 500k gates, and have successfully synthesized designs up to 5M gates.

Summary

Asynchronous logic design has been around a long time, and now we see Tiempo IC bringing their own IP, services and EDA tools to a larger audience by using SystemVerilog as an input language.

Questions:

Q: Who would use your tools?

A: Our end users are chip designers at the gate and transistor levels.

Q: What does your tool do?

A: It’s a simulator for temperature on ICs. As a chip operates it dissipates power which then heats the IC which is non-uniform across the die. It can pin point the exact XY location of your heat issues.

Q: What does the simulator take into account?

A: It understands the thickness of the chip plus other foundry-specific details to ensure accuracy.

Q: When I get a PDK from the foundry does it include the info to run your tools?

A: No, the PDK doesn’t have our thermal info yet. The fabs have provided that data to us, and we provide it to users.

Q: Which power analysis tools do you integrate with?

A: All of the major EDA vendors: Cadence, Synopsys, Mentor, Magma

Q: What types of thermal analysis are there?

A: Two types: steady state and transient thermal analysis. The transient is most accurate.

Q: How do I know that the thermal results are correct?

A: Customers have run test chips to correlate actual results with simulated.

Q: What OS do you support?

A: Linux mostly.

Q: What capacity does this tool have?

A: We have customers running billion transistor designs with our tools. You can break up larger designs into pieces to speed up simulations too.

Q: What types of IC designs really need thermal analysis today?

A: High precision analog, for example a differential amplifier must have balanced inputs to perform correctly and the current sources to the differential pairs require precise matching. Any thermal difference in these sensitive circuits will produce incorrect results.

Q: Do reliability engineers run this tool?

A: Yes, both reliability and design engineers run this tool.

Q: What is the methodology to use the tool?

A: We see that IC designers run the thermal analysis tool many times from concept to tape out. We have a few case studies (Data Channel Amp, Mobile Transceiver) for more details.

Q: Is thermal analysis similar to other EDA tools?

A: Yes, consider the analogies with timing analysis. With thermal analysis we also have aggressors and victims, where a victim net or MOS device is sensitive to a temperature change caused by a nearby aggressor device. Power management chips really need this kind of analysis.

Q: How is thermal analysis related to Electromigration?

A: EM failure is caused by high temperatures, so we can show you where to find your thermal issues before tapeout to save you spins and money.

Q: Can your tools analyze stacked dies?

A: Yes, with stacking we see an even greater need to analyze the thermal results to ensure safe operation.

Q: What about TSV (thru Silicon Vias)?

A: Yes, we can analyze that structure too. Consumer devices like cell phones are using thinner dies and stacked dies to keep sizes small.

Actually, many EDA companies have a long-term vision to be philanthropic and encourage a love for science in our younger generation. This month I was invited by Mentor Graphics to attend an event at OMSI, the Oregon Museum of Science and Industry. There is a new exhibit all about the process of designing things, so Mentor Graphics is one of the sponsor exhibits.

A local semiconductor company Triquint was also an exhibit sponsor.

I was really hoping to see something about IC design or EDA software in the Design exhibit, but alas the focus was more on the process of designing and creating in non-electronic ways. Hey OMSI, let’s showcase some of our high-tech resources here in the Silicon Forest.

Gordon Vreugdenhil, the Director of Architectural Initiatives for ModelSim was at the event and we chatted a bit.

Gordon Vreugdenhill (Mentor), Daniel Payne

I was fascinated to learn that ModelSim and other RTL simulators don’t really exploit multi-core CPUs. What struck me as odd was that SPICE simulators have figured out how to exploit mult-core CPUs to enable simulation speed ups, so why not RTL simulators? I kind of thought that digital simulators would be easy to exploit parallel processing compared to analog simulators. Hmm, sounds like an opportunity to me, especially since Synopsys has multi-core in their VCS simulator.

Cadence has a charitable side too, with the annual Stars & Strikes to raise money.

Synopsys encourages volunteers to help charities world-wide.

Finally,  Magma is charitable across many events:

• Stars & Strikes (Cadence event)
• Local food banks
• Toys for Tots
• Disaster relief (Iran earthquake, Puket tsunami)
• Active military duty assistance
• Relay for Life (American Cancer Society)
• Myeloma Research Fund
• Daughter of Erach Desai, cancer fundraiser

(Thank you Nanette Collins and Milan Lazich at Magma for an update)

Here is the opening line for Synopsys:

Synopsys, Inc. , a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that San Francisco State University is the latest university to receive the Charles Babbage Grant from Synopsys.

Further down in the press release we have the familiar EDA acronym being used in the company summary paragraph to preserve orthodoxy:

Synopsys, Inc. (Nasdaq:SNPS News) is a world leader in electronic design automation (EDA), supplying the global electronics market with the software, intellectual property (IP) and services used in semiconductor design, verification and manufacturing.

And the second press release from Magma opens without EDA as:

Magma Design Automation Inc. , a provider of chip design software, today announced Chief Executive Officer Rajeev Madhavan and Chief Financial Officer Peter S. Teshima will speak Nov. 8, 2010 at the TechAmerica AeA Classic Financial Conference, to be held in San Diego.

Like Synopsys, we still see Magma using the familiar EDA acronym in their corporate summary:

Magma’s electronic design automation (EDA) software provides the “Fastest Path to Silicon”(TM) and enables the world’s top chip companies to create high-performance integrated circuits (ICs) for cellular telephones, electronic games, WiFi, MP3 players, digital video, networking and other electronic applications.

This got me to start thinking about the other EDA companies so I checked out the latest Mentor Graphics press release from November 1 and found NO use of EDA at all:

Mentor Graphics Corporation (NASDAQ: MENT) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the world’s most successful electronics and semiconductor companies.

Of course Cadence has embraced the EDA acronym with a twist by adding the 360 phrase to become EDA360 their newest initiative:

This approach represents a stark turn from the discrete and compartmentalized ways semiconductor and systems companies have traditionally achieved Silicon Realization, the term that refers to all the steps required for bringing a design to silicon and a key component of the EDA360initiative.

Finally I visited the web site of Apache Design Automation to look for the phrase EDA in their press releases but found NO such uses.

Apache Design Solutions, the technology leader in power integrity and noise closure for chip-package-systems (CPS) convergence, today announced that Exar Corporation (Nasdaq: EXAR) has chosen Apache’s PowerArtist, RedHawk, and Totem platforms for comprehensive power, noise and reliability solution from RTL to sign-off, including analog and mixed-signal designs.

Going one step further, when you use the Search feature of the Apache web site and look for EDA, this is the result:

Long live EDA, no matter what marketing name we choose to call it.

The Americas region is still the largest sales territory however APAC grew the most by 41.7%.

Our industry is still in a slump after the peak of 2008:

I’m a little bit encouraged that EDA is treading water in 2010 and always envious of the big semiconductor companies posting record profit increases.

My hope is that the successor to CMOS technology will usher in a new era of double-digit growth to the EDA industry as IC designers need new tools to deal with the new nano-technology. History has shown that the incumbent software companies rarely catch the new technology wave in time and simply disappear because they are no longer relevant.

Google search told me that thousands of other HP Pavilion users had the same defect – a faulty Nvidia graphics chip solder connection to the motherboard. There’s even an entire web site forum devoted to all things wrong with HP at www.hplies.com

A quick call to my local HP laptop repair place in Beaverton confirmed the technical issue and a reasonable $260 repair bill for a new motherboard and labor to install it.

We all love our laptop computers however when the reliability rate becomes so poor because of thermal and other technical issues it causes me to wonder when the consumer electronic companies will design their devices with an improved reliability rate.

SquareTrade did a reliability study on laptops and found that on a sample size of 30,000 units that you could expect that 31% of laptops fail within 3 years of purchase. Here’s a malfunction chart with different brands of laptops showing that HP was least reliable and Asus most reliable:

On the EDA side of things I’m wondering if there is any software that would’ve predicted this thermal issue with the Nvidia GPU chip soldered to a motherboard. I’d love to hear from my readers if there are any EDA tools out there that take into account thermal reliability for something like a laptop system.

How could my SPICE simulator be giving more the wrong results?

What could I trust in my EDA tools?

Fast forward to the present day, 2010 and we read some lively debate going on between Cadence on one hand and un-named EDA vendor(s) on the other who have integrated their tools into the OA database.

Members of the iPDK alliance want their cells to be opened up in the Cadence Virtuoso layout tool without any error or warning messages however Cadence is resolute in displaying a warning because of past bugs with OA integrations.

The premise of OA (Open Access) is both altruistic and pragmatic, I fully support it in order to grow the size of the IC design market place and offer EDA users some choice in their IC tools along with the promise of interoperability. The list of IPL Members (Interoperable PDK Libraries) is growing:

• Accelicon
• Agilent
• Altera
• AWR
• Ciranova
• Empyrean
• Grid Simulation Technology
• Helic
• Jedat
• juspertor
• Lfoundry
• Magma
• Mentor Graphics
• Mephisto Design Automation
• Micrologic
• MicroMagic
• Parallel Engines
• Pulsic
• Pyxis
• Sagantec
• Springsoft
• STARC
• ST
• SynCira
• Synopsys
• Tanner EDA
• Tower Jazz
• TSMC

I just hope that Cadence and the OA integration vendors get resolution and cooperate in order to serve the IC design community better as a whole.

I’m delighted to see that Intel is investing in new EDA companies and it kind of hints that perhaps the big four established EDA companies are under-serving the transistor-level IC layout market place.

In the old days the transistor-level circuit designers would throw their netlists over the wall and then the layout group would pick it up, do a layout, and throw it back over the wall. This implies a certain number of iterations and some inefficiency.

Ciranova simply places a lot of layout automation power in the hands of the circuit designer so that they can get decent layouts quickly, then do simulations and tweaks without needing as many layout people.

Ciranova Helix

The other innovation that Ciranova offers is a more efficient way to write analog or digital cells using the Python language:

Ciranova PyCells

To deal with the installed base of Cadence Virtuoso users the folks at Ciranova have figured out how to use the OA database and co-exist with Cadence SKILL PCells.

This classic strategy of embracing the de-facto standard and then extending it is a winner for Ciranova and the IC industry as a whole.