This year was a true whirlwind trip to DAC for me because I arrived on Sunday and departed on Monday evening. I managed to visit with the following companies:
- Tela Innovations
- Micro Magic
- Tanner EDA
- Altos Design Automation
- Berkeley DA
- Mentor Graphics
During lunch on Monday I attended the IPL Alliance (Interoperable PDK Libraries) seminar to learn how Foundries and EDA companies are creating an alternative way to creating PDK Libraries one time that work for all tools. This is a good idea backed by a working demo this year. TSMC, CiraNova, Magma, Springsoft, Synopsys, AWR and Mentor Graphics know what they are doing by cooperating and Cadence should simply join the alliance.
Luncheon attendance was over 150 people and there was a sense of urgency and vision within the group. I think that their vision will ultimately succeed.
Sunil Shah the CTO didn’t want to talk with me and I couldn’t find Anjaneya Thakar, CEO this year and John Yelinek is no longer the Sales VP. John is a smart guy and has a good track record of selling in EDA.
No customer logos to talk about yet, so I feel that this company needs to prove itself soon to be credible. I love the idea of using multiple HSPICE licenses to simulate large designs quickly but they still have to prove the viability in a product that works as advertized.
I worked with Anjaneya at Intel.
I met with Leslie Lander, VP of Sales and Marketing. (Teo Yatman moved from Sigrity to Physware, and used to be the Sales guy at Sigrity). Brad Brim is a very knowledgible tech guy that I’ve talked to in years past.
This company offers EDA tools for: power integrity, IO planning, chip package board, SSO, package layout, current density, co-design, extraction, IR drop, decoupling capacitor optimization and signal integrity.
What’s new this year?
Three things: Optimize PI, release v8.0 and over 170 customers installed worldwide.
Optimize PI has 16 customers so far and won an EDN hot products award, this tool allows you to optimize the number, size and placement of decoupling capacitors on a PCB. Either a board or SI designer can run the tool. Pricing starts at $100K, OS support for Windows or Linux.
Release v8.0 is now shipping and has a workflow GUI that supports both first-time users and expert users.
Most impressive to me was that 170 customers are using Sigrity tools. About 60% of these customers are in North America, while international has a faster growth rate.
While the Ansys/Ansoft merger takes place look to get a good trade-in deal at Sigrity. Ansoft is a worthy competitor. Mentor and Cadence tools for SI and PI are more aimed at pre-layout analysis while Sigrity is used for post-layout PCB designs.
Parallel and distributed computing is now supported to speed up simulation and analysis times. Multi-core support is available without extra charge up to 4 cores. Networked licenses are also available.
I talked with Shufan Chan, founder. They have an analog place & route tool called ALIS (Analog Layout Integrated Synthesizer) that works at the transistor level. Their tool has it’s own framework and reads in: SPICE, lef, def and ASCII files. In the future they could run inside the Cadence environment.
This P&R tool for analog enforces design rules and produces a correct-by-construction layout for designs up to 10,000 devices. A few hundred devices will P&R in just minutes.
Platforms supported are Linx for now, Solaris possible in the future.
An early stage company with one active customer, look for a press release and more details later this year.
Competition is Cadence in a limited way, and possibly Analog Rails. They plan to read in Pcells and have their own Pcell generators. GDSII is used today. This P&R isn’t intended for RF designers. Pricing is TBD.
Neal Carney the VP of Marketing told me that Tela is a Spanish word for canvas , fabric or regular patterns. Neal met the founders at VLSI Libraries and hopes to grow another winner.
The motivation for restricting IC layouts at 45nm and below is to improve yields and reduce mask costs, and save time. They are working with Qualcom at 45nm and an unnamed foundry, I’ll guess that to be TSMC.
Tela is not selling a complete library solution today, and are partnering with the Qualcom library development group. Potential users of Tela libraries would be anyone creating libraries like the IDMs.
They’ve got patents pending on their one-dimensional layout scheme. An imressive chart showed how a test chip with Tela layout showed a 47% reduction in leakage current compared to traditional two-dimensional layouts. This approach should require less OPC software, saving you more time and money. Predictable layout patterns help simplify the overall flow, lower costs of mask sets, and even reduce the inspection times for masks.
Running a Tela layout through the Brion OPC product will complete much faster than a traditional IC layout. From a mask-making viewpoint when double-patterning is used on a Tela layout it’s a much easier process than for 2D layout.
The business model at Tela today is consulting services and eventually will grow into IP licensing, maybe something similar to what Artisan did. Foundries have to use 2,000 pages to communicate how to properly layout an IC in 2D which is simply overwhelming, while 1D layout like Tela offers a streamlined alternative.
This company is about 20 people and is located in Campbell, CA. Before Artisan the founders worked at Silicon Compilers, also located in Campbell, deja vu.
Cadence has udpated their NanoRoute P&R tool to work with the Tela 1D approach of preferred direction routing, eliminating orthogonal routing on the same layer.
Amit Gupta, President and CEO talked with me on Monday about Solido Stat their statistical variation tool for circuit designers that use SPICE simulators.
Traditional circuit simulation techniques like Monte Carlo produced very accurate results but very slowly. Corner-based simulation produced less accurate results and very quickly. Now Solido Stat launches SPICE simulations that promise to be both very accurate and very fast.
To accomplish this the foundries provide special process variation information and mismatch data. Solido Stat launches and controls multiple SPICE simulations and can provide the user with numerical and graphical output.
Pricing is TBD, platforms are Sun and Linux, SPICE simulator support: Spectre, ELDO, HSPICE.
Early customers include: Qualcom and UMC.
If you’re still running SPICE with corner-based models, maybe it’s time to check out Solido Stat. This technique would benefit analog and memory designers to simulate the effects of process variation in the most efficient manner. Amit’s previous start-up Analog Design Automation was a success and then sold to Synospys, so I wish him all the best in this start-up.
Bala Vishwanath, President and COO chatted with me on Monday morning about his Seattle-based startup. The technical core is a high-speed 3D EM solver for SI, PI and EMI analysis of boards and packages.
Their PhysPack tool is true 3D producing Maxwell accurate results, unlike other tools that use only 2.5D models and are less accurate. Another benefit is linear scaling on order N for both run-time and RAM usage.
The true parallel approach uses shared memory while other approaches just run different frequency analysis on different CPUs which then consume much more RAM. Tool pricing starts at $50K and is based upon 4 cores, and distributed processing is sold in groups up to 10 machines.
PhysPack is both easy to learn and use, automating the tedious task of creating boundary conditions setup and port setup. This one tool can be used for both package and board use instead of buying separate tools.
Runtime speed ups are design dependent however a range of 5X to 100X has been demonstrated. 3D EM competitors include: Ansoft, CST and Sigrity.
I saw about a dozen employees at DAC and they have a new VP of Sales, Teo Yatman, formerly with Sigrity. Teo says, “We do real 3D here.”
(disclaimer: I consulted for Physware in 2007)
Mark Mangum, Sales Manager met with me in their booth on Monday.
They provide the highest capacity IC layout editor (1 trillion devices) around and new for this year is support for OA – Open Access, and they joined the IPL Alliance. Check out their free viewer, some 150 companies did so in the last year.
Even before supporting OA the Micro Magic database was pretty open because it used an ASCII format. That reminds me of the popular Viewlogic database in years gone by.
Expert users can program with an API for even higher database performance and you can customize the editor with Tcl/TK.
Customers include: A microprocessor company in Austin, a router company in Silicon Valley, Juniper, Tezzaron and several smaller companies. The cool thing with Tezzaron is that they use 3D IC stacking with TSV (thru silicon via) connections and the Max editor supports this 3D view and editing.
Kathy Hayes is another technical person at Micro Magic, we worked together at Silicon Compilers.
I spoke with Edmond Macaluso, President and co-founder.
They have a tool called ZChar that can fully characterize a FF in just one minute instead of 20 minutes with other library generation tools. Library developers at foundries or IDMs would want to use ZChar.
Inputs are SPICE netlists and supported SPICE simulators are: HSPICE, Spectre, Eldo, HSIM.
Both multi-core and networked computers work with ZChar. Pricing starts at $55K for a one year term licnese, and changes for multi-core and networked-based. Linux and Solaris are the two OSes.
Their first 4 years were mostly design services and they’ve been shipping ZChar since 2005. Competitors include: Synopsys (NCX), Magma (Silicon Smart) and in-house tools.
Customers include: Numonyx, Miradia, Spansion, Infineon.
With ZChar you can characterize three types of library cells: Memory, Standard Cells, IO Cells. They even support statistical libraries like for PrimeTime VX.
Dino Caporossi, VP of Marketing spoke with me about OmegaSim GX their GPU accelerated FastSPICE tool which is 4X to 10X speedier than a non-GPU approach. Lots of evaluations in process and a couple of early customers.
Last year we heard about OmegaSim a hierarchical FastSPICE tool with 10X faster performance than: HSIM, NanoSim, UltraSim or ADiT. About a handful of customers using OmegaSim now.
Both HSPICE and Spectre input netlists are accepted. Output waveforms work with: Vera Tools, Novas, SandWorks, tr0 and FSDB.
Biggest news from last year is that Intel Capital invested in Nascentric.
Rahm Shastry is the new CEO in the last year and we worked together at Viewlogic.
Massimo Sivilotti, Chief Scientist talked with me about their broad set of tools: Schematic capture, simulation, physical IC layout, DRC/LVS and parasitic extraction.
Their SPICE simulator is called Tspice and it’s multi-threaded and works with Verilog-A models. Starting at just $5K it even support multi-core. That’s about 1/4th the price of other SPICE simulators from Cadence, Mentor and Synopsys.
You can use Tspice in GUI or command line modes. S-Edit creates schematics and is integrated with Tspice. They support both Windows and Linux.
Users are mostly analog and mixed-signal IC designers.
They have parameterized layout generators called Tcells which compete directly with Pcells. No support yet for OA or IPL Alliance. Mosis, EuroPractice and Xfab support Tcells in a PDK.
After 20 years in business Tanner EDA is still private and profitable.
Mike Demler, HSIM/NanoSim Marketing met with me on Monday.
New in the last year are multi-thread and multi-core support in both HSIM and NanoSim with no extra price incrase for multi-threading. Intel also announced that Synopsys is a primary vendor and use both HSIM and NanoSim, even replacing internal circuit simulators.
Matsushita was another large customer announcement in the past year.
Both HSIM and NanoSim live on at Synopsys, serving slightly different users. HSIM sees action with memory designers and post-layout analysis, IR drop and electromigration.
NanoSim is often used with co-simulation to Verilog VCS.
Competitors like Berkeley DA are using a PLI 2.0 approach for HDL co-simulation which will be slower than a single executable.
Synopsys is still #1 in the FastSPICE market for total seats, Cadence is probably #2 with UltraSim, Berkeley DA is #3 with Analog FastSPICE, Mentor is #4 with ADiT, and Nascentric could be #5 with OmegaSim.
Altos Design Automation
I met with Jim McCanny, CEO. They offer a tool called Variety that creates libraries for statistical timing tools like Cadence ETS, Extreme DA and PrimeTime VX. Their Liberate product creates corner-based libraries.
TSMC uses Altos tools in their 45nm library development, replacing internal tools and Cadence tools.
Other customers include: Renesas, TI, Virage Logic, Intrinsity, HP, Xilinx, Design 2 Silicon.
With a dozen or so employees this focused company is on a roll at serving customers at 45nm and smaller, while Magma has more seats in the older nodes.
Alok Hehrotra, VP Sales talked with me about this IC layout migration company that has tools that migrate digital, analog and mixed-signal designs from one node to another. I remember this company from back in the 90’s when they offered silicon compilers.
Customers include: Large microprocessor company in CA and OR, Qualcomm, Japanese IDMs, Korean memory, ST, Infineon, Qimonda.
Their migration tool works with GDSII, OA or DFII data. With just under 20 people this privately held company has survived over a decade in EDA by morphing into a migration product company. Their main competition is old-fashioned manual layout migration.
KT Moore and I talked about FineSim PRO a Fast SPICE tool and FineSim SPICE a traditional SPICE simulator.
This year what’s popular is multi-cpu support for both the PRO and SPICE tools because they reduce run times.
Customers include: Maxim, AMD, Toshiba, NVidia.
FineSim PRO competes with HSIM and UltraSim simulators.
To co-simulate with and HDL they use a VPI socket. Verilog-A is supported by both PRO and SPICE tools. VHDL co-simulation will be added later this year, so stay tuned for details.
Pricing is based per CPU core and uses time-based licensing. Linux is the most popular OS and it seems that Solaris is going away.
Titan can be used for schematic capture and IC layout at the transistor level and is tightly integrated with both FineSim PRO and FineSim SPICE. Waveforms are viewed with: FineWave, SandWorks, tr0, Cadence or FSDB formats.
About 100 seats in use for FineSim circuit simulators.
I met with Glenn Crosby, Senior Analog/RF AE.
They supply a tool called Analog FastSPICE which perfectly describes its function. Capacity for this flat simulator is maybe 10 million elements before you run out of RAM.
New in the last year are a noise analysis option that fits on top of Analog FastSPICE and co-simulation with Verilog simulators. Verilog-A is a standard feature.
Customers include: Qualcomm and Broadcom.
Licensing is based on tokens. One token sells for $50K and allows you to simulate up to 50K devices, two tokens simulate up to 500K devices, and three tokens for unlimited capacity. Tokens are bought annually or can be use for peak.
Linux and Solaris are both supported.
Mentor – FastSPICE
Ahmed Eisawy, TME and I met in the booth to chat about ADiT a FastSPICE circuit simulator acquired from Taiwan. Their focus is to bundle ADiT as part of AdvanceMS a behavioral language simulator.
In the product roadmap expect to see: IR drop analysis and multi-rate technology.
Mentor – IC Layout
I met with Ron Tinnel, Product Marketing Manager for IC Station. We worked together at Mentor.
IC Station supports OA today, but not Pcells. Instead, Mentor has their own device generators written in a language called Ample. Foundries work with Mentor to create PDKs.
Mentor is a member of the IPL Alliance however it’s the Calibre group, not the IC Station group.
This year IC Station has a revamped GUI to make it modern, efficient and easy to learn. It even supports tabs, much like FireFox or IE.
Customers include: ON Semi, Vitesse, Canon. IC Station is used by IC designers doing full custom design, IDMs, and is part of the UMC reference flow and has TSMC design kits.
Linux is the favored OS either 32 or 64 bit.
Apache Design Solutions
Yukari Ohno, Sr Director of Marketing talked with me on Monday afternoon in their suite.
This company has a focus on power, noise for SI and thermal integrity. Their tools are used by chip designers and package/PCB designers.
With the acquisition of Optimal they are now serving the package/PCB design market for SI, PI, noise and reliability for package/board. The Optimal agreement with Cadence continues in full force for APD users.
For co-design of package and SOC they have a seamless integration. PakSiE models for packaging are used in Redhawk tools for SOC.
In the package analysis area the big competitor is still Ansoft.
This company reports very good quarterly increases in sales and profitability, so I still think that they are best positioned for an IPO or acquisition. With over 100 people they are a leader in SI and PI.
Customers in the Apache booth presenting were: Broadcom, IBM, ST, TI, Toshiba, TSMC.
Linux and Solaris are the OSes for Apache tools, while the Optimal tools run on Windows. Time-based licensing is offered and there are no price changes for Optimal products.
Sentinel PI is their new co-design tool for package and PCB designers. The Chip Power Model (CPM) was a 2007 EDN Magazine Award winner.
Sentinel TI does thermal integrity for chip in package. Gradient kind of competes for chip-level thermal analysis, while Ansys has a thermal tool for system level.
Sentinel PI does power integrity and is in Beta right now. This tool is used by a package or PI designer. Using CPM you can see a dynamic distribution across an IC. Pricing starts at $35K.