I’ll never forget the shock when I ran some SPICE simulations as a new college graduate working at Intel and my 5V part had a circuit that doubled the VCC supply towards 10V internally to boost the Word Line on a DRAM. The waveforms were plain as day, and the boosted signal didn’t stop at 10V it just kept climbing with each new memory access. I ran down the hallway to show this to a senior circuit designer named Clair Webb and he chuckled and then surmized, “Oh, that’s gotta be a bug. Go talk to the SPICE developer and he’ll fix it for us.”

How could my SPICE simulator be giving more the wrong results?

What could I trust in my EDA tools?

Fast forward to the present day, 2010 and we read some lively debate going on between Cadence on one hand and un-named EDA vendor(s) on the other who have integrated their tools into the OA database.

Members of the iPDK alliance want their cells to be opened up in the Cadence Virtuoso layout tool without any error or warning messages however Cadence is resolute in displaying a warning because of past bugs with OA integrations.

The premise of OA (Open Access) is both altruistic and pragmatic, I fully support it in order to grow the size of the IC design market place and offer EDA users some choice in their IC tools along with the promise of interoperability. The list of IPL Members (Interoperable PDK Libraries) is growing:

  • Accelicon
  • Agilent
  • Altera
  • AWR
  • Ciranova
  • Empyrean
  • Grid Simulation Technology
  • Helic
  • Jedat
  • juspertor
  • Lfoundry
  • Magma
  • Mentor Graphics
  • Mephisto Design Automation
  • Micrologic
  • MicroMagic
  • Parallel Engines
  • Pulsic
  • Pyxis
  • Sagantec
  • Springsoft
  • STARC
  • ST
  • SynCira
  • Synopsys
  • Tanner EDA
  • Tower Jazz
  • TSMC

I just hope that Cadence and the OA integration vendors get resolution and cooperate in order to serve the IC design community better as a whole.