Archive for June 16th, 2010

Overview
Notes
PathFinder – ESD integrity for advanced electronic circuits
What is ESD?
ESD for an IC at an IO pad. How do you protect your IC layout?
Failure – breakdown of interconnect, junction or gate oxide.
Protection – ESD protection, clamp cell. Make the discharge go through a known path. Placement of [...]

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CyberEDA – PCSIM

Posted in June 16th, 2010

by Daniel Payne in Analog Fast SPICE, DAC 2010, SPICE circuit simulation

CK Lee, CEO of CyberEDA
History – Epic, Synopsys, Nassda, Synopsys
Analog Design Debugging System (ADDS) – Helps IC designer to find bugs, RC values, compare simulation results.
- Still in beta stage right now
Yong Dai, President of China branch (PhD EE, Cadence, Synopsys)
PCSIM – Parallel Circuit SIMulator
- True SPICE simulator without Fast SPICE approximations (sounds similar to [...]

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Legend Design – MSIM, Turbo MSIM

Posted in June 16th, 2010

by Daniel Payne in DAC 2010, Fast SPICE, SPICE circuit simulation

Who
You-Pang Wei, President of Legend Design

MSIM – SPICE simulator for IC and PCB, IBIS verification. Able to simulate RF, Std Cells and LCD (using Hybrid models). Measured data can be used to correct deficiencies in standard SPICE models. Used by the memory characterization tool mostly and can be used stand alone.
Turbo MSIM – Fast SPICE [...]

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OVM and UVM

Posted in June 16th, 2010

by Daniel Payne in DAC 2010

Crowds of engineers were interested in OVM and UVM this year at DAC.

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Interoperability Breakfast – Synposys

Posted in June 16th, 2010

by Daniel Payne in DAC 2010, OpenPDK, iPDK

Overview
For the past several years I’ve seen TSMC create the iPDK standard and seen modest adoption, then along comes Si2 with OpenPDK. Are iPDK and OpenPDK complimentary, competitive, or what?
The ST speaker says complimentary, however when I talk with some CAD managers and EDA execs the two standards sound conflicting and over-lapping.
Notes

Vincent Varo (ST) – [...]

12 Comments

DAC Photos on Monday

Posted in June 16th, 2010

by Daniel Payne in DAC 2010

No Comments

Library Technologies

Posted in June 16th, 2010

by Daniel Payne in ASIC Optimization, DAC 2010

Who
Mehmet Cirit, Founder of Library Technologies

History
I first met Mehmet at Silicon Compilers in the 80’s and have kept in touch with him over the years.

What
New product – Chip Timer, speeds up ASIC designs by building digital library cells on the fly. Uses both Solution Ware and Cell Opt tools to do design optimization. This approach [...]

1 Comment