What
Synopsys AMS breakfast.

Well attended breakfast session with about 100 people present.
Panelists at AMS Breakfast

Speakers

Satinderjiht, ARM

They use CustomSim for circuit simulation and their group does memory compilers. StarRC is used for RC extraction. The instance of memory that is generated is then simulated with CustomSim for timing, current and power numbers. Before CustomSim they used a traditional SPICE simulator on a RAM path instead of the whole RAM. No more RAM paths are required because CustomSim has the capacity for full RAM instances.

Another use of CustomSIm is for IR drop and EM analysis where any violations are shown in the GDS II layout. They had used Calibre before to pinpoint missing vias or contacts, but not now.

They plan to start using XA instead of HSIM for their memory needs. Is XA accurate enough now? Too much CustomSim tuning is required to get the accuracy they really want.

ARM sells about 1 billion processors per quarter, wow.

Yuval Shay, STMicroelectronics

High performance mixed-signal simulation

From Carolton, Texas

They started evaluating CustomSim XA about 6 months ago. They like the single speed versus accuracy control, set_sim_level. Accuracy was easy to setup, capacity is high even on back-annotated netlists, speed was good.

Benchmark needed to show that Eldo and Spectre netlists would be accepted, Verilog and transistor level simulation needed.

Results showed that XA with VCS simulated 1.4X to 5.1X faster than the previous simulation tools across five different AMS circuits (sigma delta ADCs, temperature sensors).

Simulating with XA they were able to find bugs in and ADC design like DC offset, then fixed it. A one million element ADC simulated 1 millisecond of time in just 17 minutes using XA.

Excellent correlation between previous SPICE results versus XA for a bandgap design.

Wanted:

compatibility with ELDO features (.step),

.alter with multi temperatures

setup for AMS more automated

VHDL-AMS
Analysis environment needs to be more sophisticated to support AMS testbenches

Summary: Loved the on-site support by Synopsys.

Mei-cheng Huang, AMD
High speed PHY Design Verification

Verification methodology is at both macro and chiplet (IP) levels.

They run simulations for: RTL, gate-level, power, CustomSim plus VCS.

Gate-level netlists: after P&R, from SPICE netlist, schematic logic view.

Challenges: multiple voltage domains, PLL, DLL, phase interpolator, serializer, de-serializer, link modeling, complex digital control, feedback loop between digital and analog, clock data recovery, decision feeback equalization.

CustomSim plus VCS co-simulation are being used in their verification flow. This co-simulation helps them verify the high-level behavior, verify system power-up sequences, check all analog features.

Using CustomSim plus VCS to verify 45nm designs in production today.

CustomSim XA with VCS runs about 4X faster than NanoSim with VCS simulator. They did have to convert their commands for each design to use XA, maybe 10 minutes per design to convert and tune.

XA plus VCS doesn’t support LSF dispatch with –I option, would be nice to get this working like with NanoSim plus VCS.

Aaron Barker, Oracle (Sun Microsystems)
Principal HW Design Enginer
Design For Yield Flows

Verification challenges using new models, strained silicon effects, 60 instance parameters, well edge proximity effects, aging effects, electro migration. TSMC is their foundry partner, how do we simulate variability?

TMI from TSMC improves circuit simulation times, how about working with the CMC to standardize?

Need co-simulation with Verilog behavioral blocks with SPICE.

They are using NanoSim for early behavioral and Verilog analysis, HSIM for memory instances, XA for SPICE and analog needs.

CustomSim is 2X to 8X faster than HSPICE for analog designs like their test chip (using TMI models).

Future challenges: Variation awareness in CustomSim. Want large blocks run with variations. Using .data tables in pseudo Monte Carlo kind of works however it’s no faster than HSPICE.

Process effects are driving circuit simulation needs today for 28nm. High performance variability analysis is required.

Pierluigi Daglio, STMicroelectronics

They have early access and beta testing for Synopsys simulators and roadmaps, fast bug fixing, continual reviews. They need to support IC designers doing AMS flows throughout STMicroelectronics.

Need to simulate Fast SPICE, analog and digital, plus design safety checks. CustomSim does all three of these.

FastSPICE – full chip, IP blocks, analog macrocells, fast Monte Carlo, IR drop and Electro migration, post-layout simulations.

Mixed-Signal Simulations – either analog or digital on top, full chip, donut configurations, 30 million device simulations, Verilog/VHDL/SPICE, whole system verification.

Design Safety Checks – sign off checks to find early errors or warnings, IP blocks, full chip, static and dynamic checks, user defined checks, safe operating area controls

Integration of CustomSim into the AMS Studio design environment.

They use CustomSim HSIM to simulate power up for designs using 24 million elements with a 100X speedup.

CustomSim XA plus VCS on a Flash memory showed 30X speedup over previous tools.

New uses: CustomSim XA with process variations and Monte Carlo analysis, sensitivity analysis.

CustomSim XA – transistor level full chip analysis, dynamic SOA checks, 5 million active devices. Analog designs.

CustomSim HSIM – 30 million devices, IR drop and EM analysis, accelerated post-layout simulation (PLX), largest capacity

CustomSim Circuit Check – static and dynamic checks, beta site for new PCCK product, advanced checking to prevent errors early on

Waveform display – smart and fast viewer, ACE lets them measure waveforms post-simulation, best in class

Simulation Uses – SRAM compilers, large analog IP, AMS designs with multi-million devices