Amit Gupta, President and CEO
Johnson Lau, Senior Director, Asia Sales
Kristopher Breen, Director of AEs

Amit Gupta (left)

The Solido approach is to work along side your favorite SPICE circuit simulator to produce more efficient results and analysis for PVT corner simulations, Montel Carlo analysis and Well Proximity Effects by focusing on variation awareness during the design process.


Three tools: Variation Aware IC Design Software

Why – variations  effect Memory, Std Cells, Analog, IO

Foundries – they provide models to describe process variations

Problem – to address variation is complex, time consuming and expensive to implement yourself.

Statistical Variation Solution (Monte Carlo Analysis)

PVT (corner analysis) – objective is to reduce the number of simulations required

Well Proximity Effects (useful for 65nm and smaller nodes)

Platform infrastructure has been made more robust this year, fast, reliable.

Cadence integration is stronger this year, including interactivity and ability to extend Cadence features.

Tool: Variation Designer is the platform name

PVT package (speed improvements by 50x over brute force)

2x to 10x faster for 3 sigma designs

GUI lets you manage how PVT is run

Monte Carlo Package

Proximity Package

Why use – improves IC designer productivity, fixes yield issues

Who uses – Custom IC circuit designer who uses HSPICE, Spectre, Berkeley AFS

Q: Why not Fast SPICE tools?

A: Users want the utmost accuracy so SPICE is the traditional choice.

Customers: Top 10 semi companies, foundries, 28nm and 40nm customers

TSMC – included in the AMS 1.0 reference flow qualified for 40nm and 28nm.

Cadence – co-wrote a paper with Solido, so they still compliment the tool flows.

Comparison with FineSIM PRO, Fast Monte Carlo – Haven’t really heard customers talking about their technology.

ESNUG – Qualcom user wrote extensively about the Solido tool flow and its benefits.

TSMC – They provide an AMS reference flow, variation aware custom IC design. User still has to make decisions on how to setup Variation Designer.

Training – Solido offers a jump-start training to give you a good feel for how to use the tools properly.

To fix your design to reduce variation sensitivity it is still up to the designer to make a change. Both senior and more junior IC designers can get better results using Solido tool flow.

Example – bandwidth versus gain plotted after a Monte Carlo. Their analysis can show me 3 sigma results. Extract corners will pinpoint my PVT corners automatically. It can also show effects of global and local variations.

Foundry provides models for global and local variations. An IDM can use this tool approach themselves.

Q: How are customers using the tools?

A: Some users are using this to verify that their new designs will yield better. Qualcom had a design that was fabricated and had yield issues, so variation design could pinpoint the source so they could improve.

Q: Who is using this?

A: This year even serdes, IO designs, memory, std cell libraries, quite a broard appeal. The smaller nodes demand variation awareness.

If your parametric yield is at 70% and you want to improve it, then consider Solido.

Q: Could you optimize transistor sizes for me?

A: Not really, the designer needs to see the sensitivity to process variation then make their own sizing decisions.

Approach – incremental capabilities to the IC designer using Spectre, Hsim, Berkeley simulators.

Q: Why not get acquired by Cadence, Mentor  Synopsys?

A: We’re VC funded and growing revenues and customers.

Accuracy aware

Monte carlo – User enters the sigma level they want, say 3 sigma, then the Monte Carlo runs simulations until it reaches that level or  it tells me that 3 sigma cannot be reached after only 30 runs.

PVT – Design of Experiments (DOE),

Strategy – Analog designers get semi-automated answers so that they are still involved in sizing decisions.

New feature – PVT analysis with 1,015 combinations get reduced to just 12 simulations. Analysis shows me where I first fail against specs. Specs are anything that can be measured with MEAS statements. Fractional factorial Design of Experiments approach.

Statstical variation – this approach is bounded by

Other fields – Could you use these improvements of Monte Carlo for other industries?

A: Yes, but we’re focused on EDA for now.

Q: How do I know that the reduced Monte Carlo results are correct?

A: Each sample point is an actual SPICE result. You can run full PVT versus our approach to get confidence in the tool.

Q: Limits to adoption?

A: Educating the IC design market. The variation is defined in the foundry models already.

PVT – Just a better corner approach.

Monte Carlo – new for people just used to PVT world.

Superimpose PVT results on top of Monte Carlo to improve your understanding of yield sensitivity of each design.

Run variation tools on pre-layout plus post-layout netlists.

Barriers to clones – 10 patents filed or issued to protect the core technology and methods. Partnered with Synopsys, Mentor, Cadence, Berkeley (complementary, not competitive).

Avoid over designing, under designing with poor yields.