Brad O’Connell, VP Sales and Marketing (PolyTeda since 2008)
Vlad Marchuk, President & CEO
Ravi Ravikumar, Marketing

PolyTeda has a new DRC tool called PowerDRC that scales well with the smallest nodes at 65nm and lower, running with predictability using a unique windowed approach instead of layer-at-time approach.

Founded: 2005 as Polyteda

Cadence – Acquired Vlad’s first EDA company in Moscow, 2002/2003. Assura support in 2004.

1991 – started offering DRC and LVS on PCs not mini-computers or mainframes, used MS-DOS then OS2. Moved to Windows 2.0 and up.

1997 – moved to Canada, did 32 bit  port.

2001 – Cadence visits Moscow but sees local PC based tools from Vlad, bought the source code and created an office.

2004 – New challenges in process nodes, what should the new DRC/LVS architecture be? Left Cadence to start up a new company.

2006 – Rest of team leaves Cadence for Polyteda. Experts at writing small code, efficiency. Rule deck explosion.

DRC Market

Early DRC leaders – Dracula at 250nm, Calibre at 180nm (use layout hierarchy), Calibre/Quartz at 90nm (use parallel process), PowerDRC at 45nm (use one-shot adaptive process)

Problems of Calibre – non linear depencies

Quartz – divide and conquer with parallel processing (tapers out after 40-50 processors)

Issues – one layer at a time

New way (Power DRC) – read in multiple layers at once and check them, break chip down to a small window then move the window across the chip until completed, makes the run time linear. Still use hierarchy but not the same way as Calibre.

Power DRC – Close to Calibre run times on Memories, however with more random logic then Calibre slows way down, Power DRC doesn’t slow down.

Not a Calibre killer, however if Calibre has run time issues then come try Power DRC instead.

Calibre – Great tool down to 65nm however it starts to slow down at smaller nodes.

Predictable DRC performance – 22nm is 4.5 million transistors per hour per cpu (projected)

Calibre customer – refactoring their design to work within the Calibre hierarchy limitations

Rule decks – An explosion of rules as nodes get smaller. Created 65nm rule decks for UMC process (only Calibre is other vendor), about 20% fewer lines in rule deck compared to Calibre. Can translate Calibre rules into PowerDRC, or just have Polyteda write the rules.

AWR – Asked for GaAs rules. Integrated with Analog Office.

Focus – Primarily CMOS processes.

Results of DRC check – text and visual viewer, but not an RVE equivalent tool. Works in the Virtuoso and Laker environments.

Features – Support parallel CPU and multi-core. One license 4 cores, 2 licenses 8 cores, 3 licenses 12 cores. 2 year lease is about $200K.

OS – Support Linux, Windows XP, Windows Vista 32 bit, or 64 bit.

Beta customers – Japanese now, released in December 2009