Bradley Geden, CustomSim marketing

Dwayne Holst, Custom Explorer

Geoffrey Ying

(Packed room: 10 people)

CustomSim is really three engines: NanoSim, HSIM (memory), XA. In my view NanoSim and HSIM users need to transition to XA where all the new development is taking place.

IR Drop, EM analysis – options to CustomSim

March 2010 release – XA now 4X faster compared to 2008 release

-          HSIM, 5 to 8x faster for power-up and power-down simulation

-          NanoSim, at 45nm between 3x to 6x faster

The future – It’s the XA engine, single engine.

XA – Introduced in 2007, three years old now.

-          ST used other FastSPICE in 42 hours, CustomSim at 3.72 hours

Challenges at 28nm and 22nm

-          Number of model parameters, BSIM 4 with 800 parameters, creates more tables, uses more RAM

-          CustomSIM has a 4X smaller RAM footprint now

-          CustomSIM has more efficient tables, giving 2.5X improvement in speed

Direct Kernel Integration – between VCS and CustomSIM

-          Any netlist on top, easy to mix and match

-          Support VHDL, Verilog A, Verilog AMS, SystemVerilog

CustomSIM with VCS – between 1.4X and 20X faster based on complexity

Q:Do you use multi-core or multi-cpu?

A: Some multi-threading.

Q: Difference with FineSim PRO?

A: Similar claims for FineSim, but don’t believe the FineSIM PRO really has speed ups.

CustomSim Circuit Check – static checks, dynamic checks, programmable checks

-          Pre-simulation (floating gates, mixing level shifters)

-          Dynamic checks run during simulation (if you power down, is there leakage?)

-          Programmable (like ERC checks in Tcl)

-          How about Calibre PERC comparison? We do electrical propagation but no layout PERC.

-          ST quote: it was a life saver. Used in sign-off flow. Even running on old designs.

CustomSim Reliability Analysis – IR and EM (Q:Aware of GRID Sim? A:Not yet.)

-          Q:Difference with Apache? A: They are static checks, not so accurate but fast. Their dynamic is simplified.

-          Q: Is IR drop full chip or block? A: A few million devices, yes.

-          MOS aging


Custom Explorer: cockpit for simulators and netlist debugger

-          Released in June 2010

-          Transistor level debugging environment

-          Reads netlists

-          Soure code viewer

-          Connectivity viewer (not a schematic generator of sophisticated like Concept Engineering tools)

-          Spice linter

-          Reads: Eldo, Spectre, HSPICE netlists

-          Ability to make a snapshot of a simulation

-          See netlist hierarchy

-          Source code viewer

-          Click a node, see waveforms throughout time

-          Post simulation measurements without re-simulation

-          Helps you script batch commands using ACE library (don’t need to learn Tcl)

-          Q:Extracted RC netlists? A: Coming soon.

Waveform Compare – New tool

-          Batch waveform regressions

-          Compares any type of signal: Analog, Digital

-          Reads multiple formats

-          You supply a rule file for how to compare a signal between runs

-          Q: How is this like Novas nCompare? A: Not sure.

-          Results are shown graphically in wave viewer