Who

Vinay Patwardhan, Senior Manager, Customer Support

What

What’s New – Fast Monte Carlo, statistical simulation technique

-          Transient noise analysis

Notes
Overview – FineSim SPICE, FineSim PRO

-          FineSim SPICE: multi-cpu capability (not multi-core with hyper threading), very linear speedup

-          FineSim PRO:Fast Spice like NanoSim, HSIM, UltraSim. Does partitioning

  • Also multi-cpu
  • PRO includes FineSim SPICE

-          Both

  • Standard netlist formats (Hspice – not accuracy options, but post, scale, etc)
  • IR and EM analysis
  • Verilog and VHDL co-simulation

-          Scalable

  • Add more CPUS to get faster speeds
  • Million transistors with 16 or 32 cpus
  • Even single CPU is about 3 to 10x faster than HSPICE
  • CPU means core (finesim –np 2, for 2 cores)
  • If LSF network then give the LSF commands to use 4 cores across 2 CPUs
  • No portioning, there is a single matrix yet multiple cores or CPUs solve it
  • ADC 1.1k devices, 1 cpu 12x faster, 4 cpu, 35x
  • PLL 10K, 8x, 27x
  • Charge pump 8K, 7x, 17x
  • Large analog block, 1.7M, 15 cpus, 16 hours

FineSim PRO

-          Efficient Power net simulation

-          CPU, 150K M, 1M R, 3.2M C, 1 cpu 2 hrs, 4 cpu .84 hrs

-          SRAM: 900K M, 1.2M R, 4.3M C, 2.23 hrs 1 cpu, 1.19 hrs w 4 cpus

Timeline – 2006 Multi CPU

-          2007 FS Pro Multi CPU

-          2008 Verilog A, ADE integration, Titan ADX integration

-          15 of 20 semiconductor companies use it

-          TSMC qualified for 65nm and 40nm processes

New in 2010 – Fast Monte Carlo analysis

-          Financial industry and mechanical used fast monte carlo

-          What? Process variation parameters are increasing with smaller nodes

-          How to accurately simulate process variations?

-          Device size variation for a ring oscillator. Output waveform has a variation

-          Traditional MC varies parameters (300 simulations). Std deviation versus #of iterations. How many iterations is enough?

-          Beyond 1,000 simulations is not feasible.

-          To achieve 95% confidence level (for a 1% error) in a normal data set:

  • 1 sigma, 724 runs
  • 2 sigma, 2006 runs
  • 3 sigma 15K
  • 4 sigma 315K
  • 5 sigma, 19 million
  • 6 sigma, 3B

-          FMC dynamically samples

-          Works towards a specified goal (mean, std. deviation, probability) with a given error tolerance

-          Guarantees accuracy

-          Supports finesim parallel technology

-          Accepts industry standard parameter variation specification

  • Other simulators cannot define a goal

-          Find distribution:Y (Traditional), Y FineSim Fast MC

-          Typical iterations: 100-1000, 50-100

-          Convergence: slow, fast

-          Find probability:no, yes

-          User specificed tolerance: no, yes

-          Global/local variation: yes, yes (in tsmc files)

  • Example: clock path delay
  • TMC: 25 runs, 8.629n mean delay, 22.78p std deviation, max error ?
  • TMC: 300 runs, 8.615ns, 5.066p, ? (you still don’t know your maximum error)
  • FMC: 25 runs, 8.615n, 4.524p, <2p max error
  • FMC: 89 runs, 8.614n, 5.044p, <1ps max error
  • Example: Band gap circuit, current measurement
    • 1,000 iterations with traditional mc
    • Set a target, then fmc will reach your goal in fewer iterations
  • Example: Amplifier gain
    • Number of sims: trad 13,055, fmc 1,039
    • Math applied based on public domain papers
  • Example: Bit cell of SRAM
    • Does the bit cell flip?
    • 6 sigma analysis of a memory bit cell failure (take millions in traditional)
    • 1 cpu, 25 min
    • 4 cpu, 5 min
    • 9 cpu, 2 min
    • Estimated probability = 2.499e-12
    • 17,382 runs required
  • Pricing per cpu?

-          Summary

  • Use finesim fmc for sign-off simulation
  • 10x fewer iterations
  • Parallel technology to get done quicker

-          Transient Noise Analysis

  • Device noise limits analog/rf circuits
  • Noise would slow down circuit simulation
  • Signal to Noise Ratio and Bit Error Rate
  • White, flicker, thermal, shot simulated
    • Noise source added
  • Spectre and hspice netlists
  • Slows down simulation run times
  • Example
    • PLL: 4.57 hours (2 hours without noise analysis)
    • Q: Is noise based on anything from the foundry? A:No, it’s based on your experience.
    • I supply min and max noise frequency.
    • Multi cpu makes the run times acceptable