Who

Jeff Jussel

Jeff Jussel (middle)

What

Challenge: how to re-use analog IP?

Summary

Magma lets you use or build process portable Analog blocks using a Matlab syntax language, plus you can optimize your analog design based on constraints. The old method of optimization is based on circuit simulation, this new technique is based on a modeling language and analog optimizer.

Notes

- At 65 nm the layout effects dominate circuit performance.

- Titan ADX: create a re-usable model of your analog IP.

o Create a FlexCell: process independent version of your analog IP

o Matlab syntax of analog models

o Used for design and optimization

o FlexCell: has topology, layout, simulation models

 System/circuit model that looks like Matlab M syntax

 Physical model (layout)

 Schematic

 Testbenches

 Modular, re-usable IP

 Process independent IP

 Opamp, Voltage regulator, bandgap, linear equalizer, pipelined ADC, sigma delta ADC

o Why not Verilog A or Verilog AMS?

 Ashutosh Maukar, most designers are already familiar with M in Matlab but not Verilog A or AMS

 This is not synthesis, it is optimization

 We don’t run Matlab or need it, just using the syntax for easy learning curve

- Titan AVP

o Proximity effects change the transistor behavior

o Does a placement for quick placement effects

o Speed up closure between schematic and layout for analog

- Demo: FlexCells Library

o Two stage folded cascade opamp for pipeline ADC applications

 Specs: Gain 60db, unity gain bandwidth 200MHz, settling: 20ns

o Enter specs

o Optimize to generate sizes

o Functional verification

o Physical floorplan

o Titan: has library browser, choose a topology for opamp, see the schematic at transistor level, constraints are added to the schematic as parameters for the optimizer

 Invoke ADX to enter specs, get sizes, optimize

 ADX UI is like Excel spreadsheet for specs (Process, number of corners, VDD, etc.)

 Rich library of cells to start with

 Like designware for analog, open to anyone (mostly large companies building own libraries)

 Equation-based optimization, not simulation

 Can optimize for AC noise, dc, transient, thd,

 Simulation would be used for verification against your testbenches

 Optimize a pipelined ADC in two hours

 Ran one corner optimization in a minute

 Ran a testbench for AC analysis and DC operating point, measured results with Finesim

 Q:Over constrain design? A:Optimizer tells you infeasible results. Show you sensitivities.

 Layout floorplan can be hand placed, then avp knows about symmetry

 Support OA and IPDK (Titan verified and qualified for 28nm PDK, and AMS reference flow)

o Create your own FlexCell

 Start with a schematic

 Write ac and DC equations

 Add your design knowledge

 Regulator example with 8 devices

 Create M files (Matlab syntax, devices, netlist, KVL equations, KCL equations) and a user file

 Topology constraints added on schematic

 Write the ac equations

 Closed loop and open loop M files created

 No floorplan constrain

 Q:What about temperature and non-linearities? A: You write those effects.

 Q:How to move from Cadence? A: Just export netlists from Composer.

 Interoperable with Cadence (5.1 and 6.1)

 Write your own constraints in M syntax

- Recap

o Take opamp, optimize it, simulate to compare results verus objective

o FlexCells off the shelf, create your own, process portable (old way with simulation takes one week, done here in a minute)

o Panasonic – pipelined ADC optimized in ADX, 2 hours to optimize, 11 different versions created in 4 hours (which is lowest area, lowest power, 6 months by hand)

o Q:Schools: MIT, Stanford, UCLA, UC Berkeley (soon)

o Q: Limits? A:Analog centric, not for digital designs.

o Q:Other simulator than FineSim for characterization? A:Use any simulator or model.

o Pricing: See your Account Manager.

o Ring oscillator PLL, PCIE, SATA, XAUI drivers