Robert Hum, VP and GM for DSM Division

Eldo and ADiT update

Eldo is a traditional SPICE circuit simulator, first made popular in Europe. ADiT is an acquired Fast SPICE circuit simulator from Taiwan that replaced Mach TA a few years ago. ADiT Rail was re-launched and offers IR drop analysis and EM analysis, including viewing. Both simulators work with Verilog and VHDL languages, called Questa ADMS. Stay tuned for speed improvements with dozens of cores for Eldo.


Strategy – custom IC design focus

-          Verification simulation

-          IC Analyst

-          ADMS (Simulation between ModelSim and circuit simulators)

-          Custom IC Layout (IC Station)

Customers – Component level design (automotive, brakes, power control devices, bipolar, analog, discrete analog)

-          Embedded analog design for SOC (camera controller, usb driver, pll, serdes)

-          130nm and up, 130nm and smaller

-          Circuit simulators in each segment

  • Capacity
  • Performance
  • Accuracy

-          ADiT (Fast SPICE) – partitioning, tables, event driven tool, large D small A

  • Good for AMS devices
  • (HSIM for memories)

-          Eldo (Traditional SPICE) – characterization tool, high accuracy, digital cell libraries, analog IP blocks

  • Strong presence in Europe because the tool was developed there
  • Automotive (reliability, aging), aerospace and medical clients prefer Eldo
  • Integrity of results is attractive

ADiT Rail – full chip IR drop analysis tool with Fast SPICE simulator, helps to size power rails and vias

-          Separate from ADiT circuit simulator

-          2d color plot with hotspots

-          Re-launched the tool this year

-          ADiT came from Taiwan acquisition

-          ADiT does multi-rate for speed ups, plus tables

-          Does full-chip EM analysis

Q: Interoperability for IC tools?

A: Launched Advanced Verification Methodology (AVM), Synopsys had VRM and Cadence had E. Cadence and Mentor now have Open Verification Methodology. System Verilog was adopted

Standards can drive innovation.

Q: PDK efforts?

A: Founding member of Open PDK. Want joint ownership of the next generation spec: Foundries, Clients, EDA. Will need some encryption for the foundries to protect their IP.

iPDK works with – Created by TSMC adopted by Laker, Synopsys, CiraNova, not Cadence. What about: Global Foundries, UMC, other foundries.

Q: Open Access efforts?

A: Mentor is compatible. OA ties you to Cadence’s code. OA is an interchange format to Mentor IC station but not native. Clients should not be held hostage on data formats. OA as a an interchange works OK however Mentor tools do things that cannot be allowed in OA.

CiraNova – Robert on Board of Directors, Mentor invests, Synopsys invests.

Q: Hierarchical simulation?

A: HSIM is loosing accuracy now. Eldo has become 12 to 18 X faster in speed recently. Many designers want the accuracy over capacity . Eldo has some hierarchy features in the works, stay tuned.

Q: Infinisim has big claims in Fast SPICE, but what is their accuracy?

A: Accuracy has to suffer.

Q: Parallel simulation?

A: Most simulators saturate at 12 cores. How to exploit with more cores. Eldo can use 12 to 16 cores now, so in a year up to 70 cores.

ADiT – Multi rate is new and helps speed up results using multi-threading. They prefer AMS.

Eldo – Last 18 months about 12x speed up. Hierarchical memories another 12-18x. Characterization about 4X.

ADIT – About 13X speed up across the board, accuracy is still there.

Monte Carlo – Incremental MC is new, so you don’t have to throw anything away, just add to it. Auto stop MC until you are at a certain std. deviation.

Verilog AMS – At first was interpreted and is now compiled to improve speed. ADiT will simulate with Verilog AMS.