Mephisto

Kenneth Francken, CEO at Mephisto explained how his tools will help make analog designers more efficient by helping them to do analog IP verification, IP migration and IP creation. This Belgium-based start-up kind of competes with what the Neolinear tools at Cadence provide but then adds a more sophisticated test bench composer and automated documentation [...]

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CustomSim & HSPICE

Christopher Labrecque, Marketing Manager for Analog & Mixed Signal made a suite presentation on CustomSim which includes circuit simulators like: HSPICE, HSIM, NanoSim and XA. Fredrik Ivarsson, Senior Corporate AE demonstrated the tools running on a laptop.Slides showed that HSPICE has sped up about 5X in the past 2 years and that with [...]

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I met with Simon Butler of Methodics, along with Joe Fowler of Fowler Communications to learn about how former Cadence people started the company to help hardware designers benefit from software methodologies. They define Design Data Management (DM) as integrating Software Configuration Management (SCM) tools into the Cadence tool flow.
Instead of creating yet another SCM [...]

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What is a virtual IDM?
To me it is the collaboration of ARM, Chartered, IBM, Samsung and Synopsys as they announced on Monday morning how they are collaborating on vertically optimized technology for 32nm and 28nm mobile SOC designs. I think that this virtual IDM will find some competition from the likes of Intel in the [...]

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I’m in the Press room this Sunday morning and all checked-in for the 46th DAC. Follow all of the Tweets for the show at #46DAC from the many folks blogging this conference and trade show.

I just met John Donovan, Editor with Low-Power Design. We’re on laptops blogging, tweeting and catching up on emails.

Rick Stanton, Director [...]

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On Tuesday I spoke with Chi-Ping Hsu, Senior VP of R&D for the Implementation Products Group about the direction that R&D is headed at Cadence. In 75 minutes we covered 52 corporate slides and I quickly sensed that Chi-Ping is genuinely excited to be at Cadence and leading his troops forward in the highly competitive [...]

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If your next design has 100 million gates then what tools are you going to use for logic synthesis?
Until today you would be faced with breaking up your design into blocks and then stitching them together, hoping that your partitioning didn’t miss any critical paths that cross block boundaries.
Oasys is the newest logic synthesis [...]

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I talked with Holly Stump at Jasper by phone last week about their newest release of formal verification tools. Holly has worked before at Sequence and Precedence.
Because formal tools examine the state space of your logic design they can run a long time and take up lots of RAM, so Jasper did something about it. [...]

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I’ll be visiting the following list of EDA companies at DAC this year and writing what I learn about each one:
ACCIT – Parallel SPICE, http://www.accit-newsystemsresearch.com/
Altos DA – Cell characterization, http://www.altos-da.com/
Analog Rails – schematic driven layout, http://www.analograils.com/
*AnSyn – analog optimization, http://www.ansyn.com/
Apache DA – power, noise, reliability, http://www.apache-da.com/
*ATEEDA – analog test, http://www.ateeda.com/
Berkeley DA – Analog FastSPICE, [...]

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