I met with Dave Milman, Marketing at Ciranova on Tuesday afternoon.
Big news this last week is that TSMC is now supporting iPDKs because we are no longer locked to Cadence Pcells. PDKs from foundry supported Pcells, but then each EDA company supported their own PDKs. Now any layout editor can use iPDKs. Many different tools [...]

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On Tuesday I met with Richard Shi, Ph.D.,Chairman and CTO of Orora Design Technologies.
This company offered the 1st – optimizer and analog synthesis tool.
They showed me three tools for use by analog design engineers.
Arana – Behavioral model generator (dial in the percentage accuracy needed)
-          Bottom up generator (RTL extractor, algebraic reduction)
-          Top down generator (like [...]

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On Tuesday I had a Suite presentation from Jerome Toublanc, Principal Product Engineer at Apache.
They are a private growing company founded in 2003 with a focus on power and noise integrity for chips, SIPs and packages.
Products Include
- RedHawk – SoC Power (dynamic voltage drop) Chip Power Model (8 0f 20 top semi clients)
-   Sentinel (Optimal) [...]

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I met with Pat Drennan – CTO on Tuesday to learn more about Solido Design Automation. Pat is an ex Motorola/Freescale guy who really likes statistics and silicon device physics.
For years now the foundries provided models for Monte Carlo analysis however full Monte Carlo runs just take too much circuit simulation time to be practical [...]

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Paul Estrada, COO met with me at their booth to share how three major features have been added in the past year for their AnalogFastSPICE platform:
1) Megasolvers – These help out on large designs allowing up to 10 million elements to be simulated at SPICE accuracy on a 64 bit CPU.
2) Multi-core – Now supported [...]

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