If your next design has 100 million gates then what tools are you going to use for logic synthesis?

Until today you would be faced with breaking up your design into blocks and then stitching them together, hoping that your partitioning didn’t miss any critical paths that cross block boundaries.

Oasys is the newest logic synthesis vendor to claim 100 million gate capacity with their new RealTime Designer tool. Not only capacity but they are claiming some incredible run-time inprovements too. Don’t miss this company at DAC if you’re on the bleeding edge of gate count.

Renesas in Japan is the first named customer of the tool.

Speaking of Japan, it seems that Cadence wanted to counter the Oasys announcement last week by releasing an endorsement from STARC about their logic synthesis capacity of 20+million gates.

Competition is wonderful in EDA and I look forward to seeing who wins this highest-end logic synthesis battle.

Finally, I admire when a company like Oasys simply tells us the pricing┬á for their new tool. I don’t have to find an Account Manager, get qualified and then finally learn about the $395K annual pricing.

How long before Synopsys catches up to this capacity and speed?