I met with Dave Milman, Marketing at Ciranova on Tuesday afternoon.
Big news this last week is that TSMC is now supporting iPDKs because we are no longer locked to Cadence Pcells. PDKs from foundry supported Pcells, but then each EDA company supported their own PDKs. Now any layout editor can use iPDKs. Many different tools [...]

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On Tuesday I met with Richard Shi, Ph.D.,Chairman and CTO of Orora Design Technologies.
This company offered the 1st – optimizer and analog synthesis tool.
They showed me three tools for use by analog design engineers.
Arana – Behavioral model generator (dial in the percentage accuracy needed)
-          Bottom up generator (RTL extractor, algebraic reduction)
-          Top down generator (like [...]

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On Tuesday I had a Suite presentation from Jerome Toublanc, Principal Product Engineer at Apache.
They are a private growing company founded in 2003 with a focus on power and noise integrity for chips, SIPs and packages.
Products Include
- RedHawk – SoC Power (dynamic voltage drop) Chip Power Model (8 0f 20 top semi clients)
-   Sentinel (Optimal) [...]

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I met with Pat Drennan – CTO on Tuesday to learn more about Solido Design Automation. Pat is an ex Motorola/Freescale guy who really likes statistics and silicon device physics.
For years now the foundries provided models for Monte Carlo analysis however full Monte Carlo runs just take too much circuit simulation time to be practical [...]

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Paul Estrada, COO met with me at their booth to share how three major features have been added in the past year for their AnalogFastSPICE platform:
1) Megasolvers – These help out on large designs allowing up to 10 million elements to be simulated at SPICE accuracy on a 64 bit CPU.
2) Multi-core – Now supported [...]

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On Monday night at DAC I was treated to dinner and entertainment courtesy of Mentor Graphics. At DAC they like to invite press, customers, vendors and now bloggers like me.
A bus whisked us away from the Moscone Center to The City Club of San Francisco. Drinks and hors d’oeuvres were free flowing followed by a [...]

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Cadence Mixed Signal

Pete McCrorie and Kishore Karnane gave a suite presentation on the Virtuoso Analog Design Environment (ADE) showing how AMS Designer gives multi-level simulation of SPICE, RTL, TLM and Behavioral languages. Circuit simulators like Spectre, Spectre Turbo, APS and UltraSim can be called from the Virtuoso GUI.
Virtuoso and Encounter are now fully integrated together [...]

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ATEEDA

David Hamilton, CEO at ATEEDA introduced me to his company where they help cut the cost of testing analog pins on your IC by using conventional digital testers.
OptimATE has been around for two years and it is a software tool used by design or test engineers to make voltage measurements on your analog pins. The [...]

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Springsoft – Custom IC Layout

Duncan McDonald presented in their suite about the custom IC layout editing of Laker, along with the P&R provided by Pyxis.
Because these tools use Open Access (OA) in runtime memory there are no files to export then import again in a sequential flow, rather all the tools can be running concurrently [...]

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Neal Carney met with me on Monday afternoon to provide an update on what’s new at this hard IP company. They acquired Blaze DFM in the last year and are offering two products: PowerTrim and AreaTrim.TSMC is their exclusive partner using these new 1D layout cells that provide improved performance and yield at 65nm nodes [...]

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