The need for speed is ever present to transistor-level circuit design engineers and now Cadence offers them some instant relief with APS – Accelerated Parallel Simulator. In the press release we read from actual customers that have 10x to 20x speed ups without a loss in accuracy.
I was just curious about pricing and the press release [...]
EDA Thoughts
From an EDA marketing insider
Archive for December 11th, 2008
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