Pallab’s Place

At the recent Linley Mobile Processor Conference, they reviewed both detailed and high level trends in systems designs for the mobile marketplace.  The mobile markets are now filled with standard phones, smart phones, tablets, netbooks and laptops.  In the overview, the mobile market did not include cameras, video capture, e-readers and music players.

The major trends are towards video processing and content capture/streaming.  In order to address these characteristics and maintain the mobile use cycle, the main processing cores have to both increase in performance and reduce total power.  The direction is for dual and quad core processors are going to be replacing single core processors in most devices.

The tablet and smartphone opportunities will be high in the coming year, but smartphones will outpace tablets.  The single core phones will move to dual core and the dual cores will move to quad cores.  The quad cores will be limited to tablets in the near future.  Tablets will also see higher performance GPUs and reduction in power for the GPU performance.  The goal is to process 1080p video in a wireless connectivity environment and have this move to both 2D and 3D images.  For these applications, bigger screen sizes will be in play.

The RF side is also getting multi-format.  In addition to 4G and 3G, WiFi is becoming a ubiquitous connection for all of these devices.  The battlefield for the wireless video protocol (WiDi, Wireless HDMI, etc) is still open and will most likely be decided by minimum adherence to data format complaince and mostly driven by the lowest power envelope possible.

PC

The Smart Power Grid Technology Conference (www.spgtc.org), organized and presented by ISQED, has connected embedded systems as the underlying theme.  The conference has a diverse array of speakers covering topics from the business of converting utility ratepayers into data services customers through smart grid distribution and to at home/office smart monitoring and control.

There are two major underlying themes behind the smart grid – one is that devices which were single tasked devices with simple embedded controls are now needing connectivity and processing power to work to sensors and an UI to be able to deliver formatted data to the smart grid data aggregators.   The second is that the data once collected, has multiple tiers of value – to the homeowner, the equip manufacturers, the utility company and the country.

The one day, being held May 12th at the Biltmore Hotel in Santa Clara, features 10 speakers and a panel.  The panel discussion is on the business of the Smart Power Grid, and which sides of it have the best opportunities and jobs.  Speakers from the event include Marvell which will be discussing the use of connected embedded controller devices in a proactive role for monitoring of energy consuming products in the home.

In addition to industry speakers, several industry renown consultants and academia personnel will be presenting trends and innovation talks and challenges for the industry.

For information and registration please refer to the conference web site www.spgtc.org

pc

At the SPIE Advanced Lithography event in San Jose, Synopsys presented their current mask making solutions.  The solutions include : (A) Proteus Litho tool (OPC & LRC) for mask synthesis, (B) CATS for mask write, fracture, inspection and metrology,( C) Sentaurus for process and device TCAD, (D) Yield Expolrer/Odyssey which is a design centric yield managment tool and (E) LightTools/CodeV for optical design and analysis.  At the litho event the concentration was on the Proteus tools and the link between stages.

The delays in EUV have forced the current litho equipment to push past the 28nm node to the 20nm production nodes with the use of complex techniques such as double, triple and quad patterning.   The first use of limtited funtion EUV is now targeted for the 16/15nm node and wil require new corrections alogorithms and run time solutions.  For EUV one of the major changes is the writing of full reticles not jsut single fiels.  This changes the methodology and strategies for RETs such as DPT and MBAF (model based assist features) and how thet are put into the design.  At 16/nm the RET sequnce will include RBOPC, MBP{C, RBAF, SMO, MBAF, LELE, IMT, Spacer, LRE, and MEC for a supplement to the ArF Wet/EUV/eBDW litho flow.

The Proteus double patterning tool (DPT) solution delivers a design based compliance solutions to avoid zero yield masks, a cost based solver to minimize pinching and bridging, symmetry enforcement for better runtime and color balancing for uniformity between the two masks.  These solutions are part of a full flow for design that includes DPT awareness in placement, routing, compliance checking and fixing, creation of compliant GDSII, and DPT compliant fracture.

A major new feature of Proteus is the support Long Range Effect (LRE) for use with EUV.  These include mask shadow modeling and 3D compact models for improved accuracy and tunable short range flare parameters.  These models and the tool runs on standard x86 hardware and support pipelining on all steps. The prodcuts are currently available.

March 15, 2011 – Santa Clara, CA – The 12th annual ISQED conference (www.isqed.org) kicked off with the themes of next generation systems and applications.  The keynote “Multitechnology Hyperintegration Platform: the technology crystal ball” by Dr. Kamran Eshraghian was very engaging and well received by the early morning audience.  His discussion focused on the creation of disruptive technologies based on the SoS or System on System space.  The innovation gestation period was shown by example to be about 30-50years from creation of the concept.  This was illustrated under the timeline for the Memristor – it was theorized in 1971 and then realized in 2008, its manufacturability and integration into products is still on-going and is expeced to hit its peak in the 2020′s.

On a similar schedule, the new area of amibient intelligence – or pervasive computing and connectivity was launched in 1987 and should see initial realization in 2020, with production in 2030′s.  Another area of discussion was the creation and use of metamaterials.  These are materials with non-standard characteristics since as a negative k factor for optics.  These materials, as well as the continuing shrinking of micro designs to nano designs, will result in new interactive systems and sensors that will be largly photonic based.  Dr. Eshraghian discussed how we currently don’t have a crystal ball to show how these pieces come together, but the direction is that the technology, once mature, does make its way into the nominal consumer culture on a global basis.

On the following technology progress line, the next speaker was Dr. Fabian Pease.  His topic of discussion was “For how much longer can Moore’s Law hold?”.  His discussion focused on the actual drivers from the current technology node, and made the argument it is NOT the transistors, it is the wiring that is in the scaling equation.  The key to Moore’s law is the lithography scaling in both geometry and cost.  The 500x increase in the cost of the litho equipment is directly proportional to the 500x decrease in the cost of minimum sized devices in the process.  To make the next transistion, something radical has to happen.

In his discussion, he indicated the most significant advance in process technology since the start of the CMOS era, is the application and development of Chemical Mechanical Polishing (CMP).    The next area of development to help maintain the density scaling is to move away from the confinement of a single plane technology.  3D technology and multi-technology stacking will help push the scaling for another several decades and will help remove the direct cost proportionality with the cost of litho. In the 3D world, the mixed technology allows for functions  to be implemented with both high and low litho cost processes, that can meet the scaling rules for functionality and not exceed the cost constraints that are needed for high volume use.

The second day of the conference, Robert Patti of Tezzaron Semiconductor, gave an overview of 3D stacking technology, and their wafer bonding technology.  The method they have developed and licensed to many major semiconductor companies, is based on face to face landing pad bonding of two designs – typically processors to memory, and can contain billions of vertical connections per 300mm wafer.  The discussed the reliability of the bonds, and that thier methodology requires the application to create the test methodology based on post assembly test.  They do not run tested die on the wafer, as it introduces mechanical damage to the wafers,, instead they rely on PCM tested wafers.

PC

In its 12th year, the ISQED Conference is driving the forefront of QOE, QOR, QED and the methodology behind meeting those goals.  This years event (March 14-16 at the Hyatt in Santa Clara) features 13 tutorials, 7 keynotes, 21 session tracks, poster sessions and exhibits.  The conference has shifted the content of the event to include more discussions and papers on system level design, SOCs, FPGAs and testability/verification which are now critical functions to the user experience of the electronic prodcuts.

The tutorials topics include:

* SRAM and Logic Circuit Techniques for Low Power Design in 32nm and Below
* Automated Design and Porting of Analog/Mixed-signal Circuits
* Current and Electric Field Induced Switching of Ferromagnets for Low-power Memory Applications
* Application of Spintronics for MRAM and Memristor-based Computing
* Hybrid Electrical Energy Storage Systems
* System Level Power Management for Cellular Chipsets
* Modeling, Abstraction, and Verification of Industrial Flash Memories
* TechTuning : DFM Methodology for Stress Management for 3D TSV Products
* Stress Assessment for 3D IC performance: Full chip analysis
* TCAD Simulation for Stress Management in 3D IC
* Multi-scale materials characterization – Input for stress simulation and model validation
* Verification of Power Managed Wireless SoCs

Keynotes for the event include speakers from  Cadence Design Systems, Innovation Labs, Stanford University, Synopsys, Tezzaron Semiconductor, Marvell Semiconductor, and Mentor Graphics.  he topics range from smart meter to 3D assembly to the future of Moore’s Law.

Registration for the full conference and tutorials is still open.  There is free registration for the exhibits/poster sessions and the co-located Electronics Design Education Conference which is held on Wed 3/16 at the event.

PC

At the recent Ethernet Summit the theme was 40G and 100G – technologies that are here today.  With the large number of major semiconductor manufacturers adopting the 40nm low power process nodes, the number ot 40G and 100G system solutions are growing and being readily adopted in systems.

The standard architecture for a 40G system is to have 4 lanes of 10G at the front end.  The current incarnation of 100G is either 10 lanes of 10G or 8 lanes of 12.5G interfaces.  These are speed limited by the SERDES that create the L1 PHY that includes the transceiver.   At the 40nm node, these PHYs and SERDES can be creates with low power processes, yield well, support the lower operating voltage and be implemented in single, dual and quad SOCs.    The primary differentiation is whether the connection is made with fiber or with copper.  The standard wire specs are out and they have a lower cost of installation and per wireing but fiber has noise immunity and a cleaner signal over distance.

For increased data rates, the challenge of 25Gb channels were being discusesd for both 40nm and rebn processes.  The advent of these higher spead parts have driven up the complexity of the PHY.  The MAC is still segregated out to be revised and created seperately to support the faster movement snd revisions of the data formats and handshakes.

The discussions focused on components, cables, connector, test equipment and validation for the interfaces.  The key portion for these high speed channels is the design validation & the board level characterization.  The deployment and validation of the BER and ECC for these data rates is their key to use in the cloud server environment.

The system design for these blocks has to incorprate a validation ot the whole TCP-IP stack fron L0 (cables) through L1 (PHY) all the asy up to L7 which is applications.  The data center design – from the use of SSDs, where to implement PCIe cards, and howe to partition between CPU/GPU and SAN are now being directly related to to the selction of the PHY and MAC that bring the data to and between the racks.  These high speed applicaitons and the voracious appetite for data movment has once again restored these analog specialties to the critical path of network design.

PC

The theme for this years ISSCC (International Solid State Circuits Conference) is “Electronics for Healthy Living”.  In addition to the new microprocessors, memory and data converter technologies, the focus and keynotes are directed towards health care products.  The common theme between all the talks, are health care is being driven by mobility, information flow, and power.  The key to high quality data transfer is having enough power to complete it – either wired or wireless.  The key to mobility is to have autonomous power for the devices for the duration of time that it does not impact the activity the user is involved with.

The keynotes cover the range of silicon’s impact on the health care.  Medtronics is discussing the scope of implantable devices, the reliability, data transfer and the system architecture of the implanted and external portions of the system.  IMEC then follows with a discussion of the invasion of specialized purpose sensors that are now possible, their in-roads into health care and the creation and powering of body area networks.  Samsung then speaks on a different twist for health care.  Their discussion is that the major cause of pollution is energy consumption and hence generation.  The way to address this problem is through reducing energy use in the manufacturing process and in the design of devices that utilize less power and can take advantage of  innovative packaging.

Following the keynotes is the inaugural Plenary RoundTable discussion on how to address the next 10X reduction in power.  The discussion is is hosted by Jan Rabaey of UC Berkeley and features TSMC, Hitachi, STMicro, Infineon, IMEC and other senior experts from the semiconductor and university commnity.  This challenge, encompassing process innovation, CAD, design flows for digital, RF, analog, and memory is one of the key drivers for the next generation of energy efficient electronics.

Energy efficiency has now earned its own session with Energy Efficient Digital which will be detailing such projects as ultra-low-voltage standard cells that operate down to 62mv of supply.  Other new technologies include a 28nm DSP from TI that can operate at 0.6V, and wireless sensor processor that utilizes only 10pJ per clock cycle.

The technology development sessions once again mix between high performance and low power.  On the high performance side, architectural design for Terahertz (300GHz to 3THz) imagers and associated device blocks – amplifiers/antennas are being shown.  On the low power side , a transceiver that can operate at 0.24nJ/b, and energy scavenging converters now up to 72% efficient and generating 95mv will be presented.

Filling out the program are tutorials on Ultra-low power digital design and a forum on Ultr-low voltage VLSI for energy efficient ICs.  These sessions are expecting large attendence as they are the dominant directions for the next decade.

The shift for the conference and the industry is dramatic.  Historically – the past 40 yaers, the conference has been the platform for the biggest, and fastest semiconductors were debuted.  These devices are now having to share the spotlight with the smallest, highest density and lowest power devices.  The show is focusing a lot more on architecture, device technology and the systems aspects rather than just circuit blocks.  This focus accompanies the idea that SOCs are true systems, and the they need to be addressed as such with focus on function, performance,  power and application.  The body area network discussions and technology, which balance data transfer and power as the main tradeoffs, are representative fo the future of the systems and IC discussions in the future.

PC

On Jan 19th, the Churchill Club held a discussion and dinner on the topic of WikiLeaks – Why it matters, Why it doesn’t?  The discussion featured a diverse and very knowledge group consisting of Daniel Ellsberg – Former State and Defense Dept Offical prosecuted for releasing the Pentagon Papers; Clay Shirky – Adjunct Professor, Interactive Telecommunications Program, NYU; Neville Singham- Founder and Chairman of Thoughtworks; Peter Theil- Technology Entrepreneur, Investor and Philanthropist, founder of PayPal; Jonathan Zittrain – Professor of Law and Professor of Computer Science, Harvard University; and moderated by Paul Jay, CEO and Sr. Editor of The Real News Network.

The discussion started on the topic of the issue of privacy and transparency in the government, and the role that WikiLeaks played in it.  A unique perspective was given by Ellsberg, who related the current situation to the environment and circumstances surrounding the Pentagon Papers.  The discussion then weaved in and out of 4th amendment issues and current/historic governmental policy.

One of the major digressions in the discussion was in the area of corporate decision making and government influence.  The topic was opened with the reviewing of how a key timed call from a ranking Senator to Amazon resulted in them turning off the WikiLeaks hosting service.  This decision influenced the financial community to also turn off or reduce support for donations to Wikileaks and impact thier operation.  The issue that was discussed was what was this decision process to make these business level decisions that have politcal impact.  The current interpretation of the constitution does not cover the actions and influences of companies, only the actions of the government.  In these cases, the question was raised – are multinational companies creating their own interpretation of transparency and secrecy based on either directly or in-directly working with government to foster agendas and actions that may be otherwise regulated? The impact of these decisions have both financial and societal impact on the use community for the internet.  These decisions also drive the supply chain for security products for cloud based services and the user base and for privatized access clouds and networks.

Further discussion on this and other 4h amendment issues can be seen in the video replay of the event.

pc

At the recent IEDM conference in San Francisco, Synopsys presented an invited paper on where Technology CAD is today and the challenges for supporting future processes.  There was a short history of standard TCAD from 1D modeling to the present need for 3D models.    The conventional TCAD is based on solving device physics equations with numerical processing of Partial Differential Equations (PDE) and simultaneous equations in matrices.  These euqations are for Poisson’s eq, diffusion, heat, hydro-dynamics, density, implants and dosing, and oxidation.  This has been the baseline TCAD since the 1980′s where the models were 1D, had about 100 points in the mesh, and solved for about 200 unknowns.  In the 2010, the process complexity requires 3D models, about 1M points in the mesh, and about 10M unknowns to solved for.

An issue for TCAD has been the “reach” of the simulation also known as the “size of the sample” area.  While in the 80′s this started with a window and mesh size that did not even cover the extent of most devices, today the widow size, while still in the low microns range, now covers multiple devices.  This has driven TCAD to have to perform application specific use modeling for CMOS, memories, analog, power devices, image sensor devices, solar devices, and TSVs.  TCAD is still a mainstay of advanced process development.  A typical process development is ~$1.1B for 45nm, ~$1.6B for 32nm, and >$2B for 22nm.  The ITRS roadmap and recommended flows indicate that modeling with TCAD can reduce the costs of the development cycles by ~30%.

Advancements in current TCAD simulation can help with complex what if scenarios such as bulk vs SOI use on device stress and Hi-K metal gate with SiGe strain enhancement tradeoffs.  The resulting process variability can now be simulated for RDF (random doping fluctuations) and LER (line edge roughness) in addition to the normal targeted solutions.

The challenges come modeling the devices below 20nm.  The reality is that a 90nm process has an Leff of ~25nm, and a 32nm process also has an Leff of ~24nm, so there is very little change in the Leff scaling.  Below 20nm this stays about the same, as the channel itself does not scale.  At these geometries, the effects that additionally have to be modeled include: strain, BTBT, Chanel mobility, quasi-ballistic transport and s/d tunneling (quantum transport).  In order to solve these equations, the simulations an still take several days.

New materials are bringing new challenges, graphene and nano-wires behave under different operating equations than CMOS or traditional III-V devices.  For these devices, atomistic modeling using kinetic Monte Carlo (kMC) methods have to be employed.  In order to address the scaling toward the end of the ITRS roadmap, new material property analysis is needed and due to the scale, ab-initio computation methods on these materials have to be employed.  This means they have to start at the particle and molecule level, then move to groups and concentrations of the particles until the multi-material interactions can be simulated.

The field of TCAD is being both guided and limited by the state of development and understanding of the material characterization of elements such as spintronic materials, graphene, nano-wire materials, and other carbon based transistors.  The field of TCAD is working on computational methods to decase the effective clock time that is elapsed during the simulations.

PC

On Tues Nov 16, the IEEE Nanotech Council held a 1/2 day event on the challenges and innovation for the world of sub 20nm device processing.  Speaking were Applied Materials, TSMC, Global Foundries and Tablula.  The overall theme was that, while there are challenges, both business and technical, there are solution paths that are being sought and providing results.  The litho, fabrication and design architecture will be shifting from today to address the needs of the process, but there will be solutions available on the current schedule proposed by ITRS.

Chris Bencher from AMAT presented how there are muliple techniques to get to 15nm resolution for litho – some are available now, and some soon.  The current method is with quad-patterning techniques.  The hope for upcoming technology is the use of EUV with double patterning.  The current solution has some challenges from line edge roughness and resist material, that are addressed and improved with EUV-DP.  Di Ma from TSMC mentioned in the panel discussion, the real challenge is thoughtput for these solutions.  For production applications, these techniques need to support 60-100 wafers/per hour, and currently the techniques are not there yet.

TSMC and GlobalFoundries had a desicription of their HKMG flows that feature “gate last” for TSMC, and “gate first” for Global.  TSMC went with gate last based on optimization of 5 simultaneous desgin/device characteristics of the devices, and Global focused on optimization of 2 key aspects.   In the panel discussion, Nick Kepler of Global mentioned that he was not sure what all the fuss is about – in the past there were 30-50 fabs who all had different process flows and manufacturing techniques, now that there a only a few fabs, why the big deal if they have different flows?

Di and Nick also discussed directions in 3D ICs, stacked die and TSVs.  These technologies are progressing rapidly and are aimed at the massive interconnect problem for new designs.  The delay times through I/O is very long and the pin counts of CPU/GPU/Memory based systems are in the 5000+ range, which is impractical for traditional edge based I/O with wrie bonds.

Steve Teig of Tablua discussed that the interconnect problem was not just limited to die to die communication, but was also the major limiter in current ICs and FPGAs.  Steve discussed some of the challenges, even at advanced process nodes, of FPGAs addressing the price performance metrics currently achived by ASICs.  He reviewed some the architectural changes for FPGAs that are needed, the new architecture of the Tabula product,  as well as throwing down the gauntlet at the programming environments .  He expressed the opinion that trying to describe chips and logic design with the C programming language is not the best fit as the structure of the C-Language is not directly compatible or optimized for the way hardware is built.

The event featured a panel discusion with the four speakers moderated by M&E Tech’s EIC Tets Maniwa who lead an interactive Q&A on the timelines of some of these litho and device tradeoffs as well as expanding on the collaboration cycle for new development.

PC