Pallab’s Place

At the Flash Memory Summit in August, there was a non-Flash session dealing with new memory technologies.  It covered RRAM and MRAM also known as Resistive RAM and Magnetic RAM technologies.

The summit is well known for showcasing new technologies, in the past few years, the emphasis has been on Phase Change Memories as the leading alternate technology, and that technology has now moved into commercial production.

The Resistive RAM session (RRAM) is technologies utilizing the resistive characteristics of the Oxygen Molecule in a crystalline lattice.   The companies presenting updates were Unity, Sony, HP Labs and Adesto.  The sector actually has two base technologies – ReRAM which is the resistive oxygen, and CBRAM which is based on resistance of the conductive filaments in the RAM cell.

Unity and HP Labs discussed their movement towards the high capacity (1TB) storage of a multi-layer cross point memory.  The HP Lab product is utilizing the MEMRISTOR technology that is built using a TiO2 cell with Pt Caps.  The Unity solution is also using an Oxygen movement mechanism in their CMOX technology.   Both are targeted for high capacity active storage applications.

Sony’s Emerging Memory group discussed ther new NVM for RRAM which is based on an an electrolytic cell made with CuTe and a select transistor.  This cell was recently built as a 4MB test macro, and the results were presented in detail at ISSCC 2011 in Feb of this year.  The resulting block was able to perform data througput at 2.3Gb/s with 100ns of latency.

Adesto discussed their Conductive Bridging RAM.  This is also a RAM type device application and has a new corner on the feature optimization.  The product is targeted at tradeoff optimization for write performance, write endurance, data retention and low power operation.  The technology should be sampling in the 2nd half of 2011, and there are several customers who are awaiting the samples for their systems.

These technologies are looking to be in volume production in the 5-10 year time frame.

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As semiconductor processes get smaller, the focus has been on patterning methods for realizing these devices on the wafer.  This is not the only challenge that is facing the cutting edge of the semi industry.  An equal issue is the metrology to determine if these patterns are created properly.

Wafer metrology deals with the measurement of planarity issues, etched structure size and uniformity along with both vertical and horizontal aspects of deposited and grown layers.  A number of these steps are optical in nature and the inspection of the wafers should not exceed the time taken to create the patterns.  As a result, the same issues, variability and uncertainty that plagues litho, also plagues metrology.

At the Semicon event this year, a number of companies were showing new solutions based on particle beam technology and other techniques.  The other techniques include Photomask Metrology, SEM, Optical Linescale, and Atomic Force Microscopy and Nanoparticle Manipulation Metrology.  To help the industrial sector NIST, has also been working on this area creating references against which methods can both be calibrated and measured.

One of the biggest issues with current metrology is identifying non-destructive and non-invasive techniques for measuring in-silicon properties such as strained channels, STI, and other “engineered materials” steps that are mainstream in today’s processes.  These metrology methods are key to the continuing trend toward outsourced manufacturing, as it is the methrics upon which the wafers are sold, rather than on a functioning die basis.

Companies with major announcement in this area at the event included Nanometrics and KLA.

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Semi (www.semi.org), the group behind Semicon, has had a long history of supporting the semiconductor ecosystem – materials, equipment, test and manufacturing.  The majority of the past 4 decades the organization has focused on mainstream semiconductor circuits in Silicon and GaAs.  The large diversity of fabs that were owned and variation in process methods, made for a very large ecosystem.

Over the years the foundry model has moved into play, and there are only a few very large IDMs with new fabs, so the mainstream semiconductor manufacturing core is dramatically reduced in number.  However, Semi and the Semicon show have adapted.

This years show, not only embraced, but featured the following high growth areas, each of which requires specialty materials and equipment to product semiconductor products.  The biggest area of growth is Photovoltaics (PV) which, with the co-location of the Intersolar conference features an equal number of attendees and more exhibitors than Semicon.  Other fast growth areas include LEDs and Lighting, Flat Panel Displays (FPD), Micro-electromechanical systems (MEMS), Printed / organic / flexible electronics and related areas of in-manufacturing metrology & test along with packaging and finished product test.

LEDs (and generalized silicon photonics), FPD, and MEMS have long been staples of the semiconductor industry, but in the past, they were relegated to private shows in thier own niche ecosystem.  The direction of stacked die and 3D Ics is driving the mixed technology end products, which now need to keep these altenate technologies in the main ecosystem.  The need to keep them in the main flow is it insure the quality benefits, processing benefits and logistics benefits that have been made for CMOS are available in these technologies.

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ARM recently had an update announcement on their Mali GPU.  The RTL level core has now been licensed by 46 parties, of which 6 have released products and are royalty paying partners.  This new core is the engine in the Samsung Galaxy S2 phone.

The goal of the Mali program is to be able to deliver high performance graphics capabilities, at higher resolutions but with the same power budget.  The shifting application space is requiring the same user experience for phones, tablets, netbooks/laptops, standard display monitors and large screen. This range includes small sub 3″ displays at VGA through 60hz 4K2K displays. The performance of the displays has to compensate for the changes in memory bandwidth and the driver power for these external memories.  The GPU block is designed to be optimized for the ARM CPUs and minimize external memory calls which consume more power.  (Fig 1)

ARM Mali GPU and CPU Architecture

The multi-core design is set for large data and scaling with a DX7 style API and providing performance at levels that are DirectX11 compatible for desktops (5Gpixel/sec or 250GFLOPS)  and Open GL ES2.0 for mobile (1.5Gpixel/sec or 25GFLOPS).  In addition to these increasing data rates, to maintain image quality, there is more processing per pixel.  The same processing core must also handle use UI’s such as touch, gesture, multi-touch, 3D and other technologies that are both engaging and also provide a simplifying user experience.

ARM Mali T604 Overview

The Mali-T604 uses the “Midgard” GPU architecture. (Figure 2).  The core is scalable up to 4 cores, and supports the full profile of OpenCL, OpenGL ES and Open VG as well as Microsoft DirectX up to V11.  The key for the GPU line (which is Android OS optimized) is to be brought to market after the 2006 acquisition of Falanx, as the graphics portion of the devices becomes more dominant.  The products are entering late into the market, and hoping to catch up on the coattails of their processor core dominance.  The core is directly in the marketplace competing against entrenched products form Nvidia, Imagination Technologies, Intel, Qualcomm, Marvell and others.

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With the rise of multi-core systems and distributed computing, the performance optimization is also spreading to using both CPU and GPU as the compute engines in software.  The fundamental architectural distinction between the two are CPUs are sequential cores and GPUs are primarily parallel pipeline style cores optimized for computation.  Currently, such code is written in Fortran, Java, Python and with direct addressed functions from the GPU provider = C+ +.  Microsoft is dedicated to supporting Heterogeneous Parallel Computing across multi-core, distributed core, cloud cores and mixed CPU/GPGPU systems with a new standard extension to C+ + called C+ + AMP.  The C+ + AMP (accelerated massive parallelism) compiler should return the C+ + programming language to being, as claimed by Microsoft, the best performance/watt of any other development environment.

The AMP extension was chosen to be added to C+ + rather than C as it is a more mainstream language and the selection was to future proof the extension with the popularity of the language.  The extension is based on Lambda functions/objects and are documented as part of the C+ +Ox extensions for compute awareness.  The C+ + AMP extension is characterized by the addition of the Array_view and Restrict keywords.   The syntax for restrict(class) is to identify a parallelized  or serialized CPU.    For example restrict(direct3d) indicates execution by any DirectX11 GPU device.

To help simplify the tasks of memory mapping between multiple architectures, clearing and grouping the low level parallelization of the code, the optimally using the available cores, the C+ +AMP extensions have been included in Microsoft Visual Studio.    This allows for the full visual development and debug environment, including the suppress errors/messages, that has been the hallmark of the C+ + development.

Nvidia also showed new extensions to the CUDA primative language and the new release of Thrust v4.0.  Thrust is a CUDA library of parallel algorithms with an interface resembling the C+ + Standard Template Library (STL). Thrust provides a flexible high-level interface for GPU programming that enhances developer productivity   (http://code.google.com/p/thrust/) Thie new Thrust library allows for those using standard C+ + compilers (those not enabled with AMP extensions).  This open source high level library eliminates the details of determining the parallel granularity of blocks and threads as well as handling the getting data between the CPU memory and GPU memory and not either stranding data or operating on out of sync data.

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The EDA and design community usually looks forward to the first day of DAC (Design Automation Conference) with excitement.  Not only is it Free Exhibits Monday, but the directions for tools and issues that are being address by the EDA community with products and partners are usually announced.  These announcements focus on the capabilities of the advanced processes to actually have design support information available to designers other than those from the 2-3 joint development companies.   These announcements and the tools vendors also address the reality of which process nodes the designs are being built.  This is the usual buzz in the industry, and this year takes place on Monday June 6th.

The buzz may not be long lived as there is another big happening on Wed 6/8, which will actually have more impact on designers that promised release of tools that aren’t quite ready and IP that is not quite frozen.  The official internet launch and support of a test run for IPV6 which happens on Wednesday 6/8.   World IPV6 Day is a 24hour test run of websites, network hardware, operating systems, and ISPs to see if the new addressing scheme works.  The necessity of IPV6 is becauser we are running out of IP addresses for devices and web destinations under the IPV4 system.

This change ripples through all levels of the design hierarchy, and the larger address size will end up impacting throughput, performance, memory cycling, effective response time and connectivity handshake for any wired or wireless device that needs to have network connectivity.  The change effects products in production and in early phase design, because the IPV4 compatibility is not permanent, and has to be upgraded to the new IPV6 stadards for long terms use.   Details on the switch and the new specifications can be found at The Internet Engineering Task Force web site,  the spec itself can be found at http://www.ietf.org/rfc/rfc2460.txt .  The fundamental changes is IPv6 increases the IP address size from 32 bits to 128 bits.  There are a number of other details, but that shift is the major one which will effect embedded and custom designs.

These two events, are going to make for an interesting June.

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At the recent Linley Mobile Processor Conference, they reviewed both detailed and high level trends in systems designs for the mobile marketplace.  The mobile markets are now filled with standard phones, smart phones, tablets, netbooks and laptops.  In the overview, the mobile market did not include cameras, video capture, e-readers and music players.

The major trends are towards video processing and content capture/streaming.  In order to address these characteristics and maintain the mobile use cycle, the main processing cores have to both increase in performance and reduce total power.  The direction is for dual and quad core processors are going to be replacing single core processors in most devices.

The tablet and smartphone opportunities will be high in the coming year, but smartphones will outpace tablets.  The single core phones will move to dual core and the dual cores will move to quad cores.  The quad cores will be limited to tablets in the near future.  Tablets will also see higher performance GPUs and reduction in power for the GPU performance.  The goal is to process 1080p video in a wireless connectivity environment and have this move to both 2D and 3D images.  For these applications, bigger screen sizes will be in play.

The RF side is also getting multi-format.  In addition to 4G and 3G, WiFi is becoming a ubiquitous connection for all of these devices.  The battlefield for the wireless video protocol (WiDi, Wireless HDMI, etc) is still open and will most likely be decided by minimum adherence to data format complaince and mostly driven by the lowest power envelope possible.

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The Smart Power Grid Technology Conference (www.spgtc.org), organized and presented by ISQED, has connected embedded systems as the underlying theme.  The conference has a diverse array of speakers covering topics from the business of converting utility ratepayers into data services customers through smart grid distribution and to at home/office smart monitoring and control.

There are two major underlying themes behind the smart grid – one is that devices which were single tasked devices with simple embedded controls are now needing connectivity and processing power to work to sensors and an UI to be able to deliver formatted data to the smart grid data aggregators.   The second is that the data once collected, has multiple tiers of value – to the homeowner, the equip manufacturers, the utility company and the country.

The one day, being held May 12th at the Biltmore Hotel in Santa Clara, features 10 speakers and a panel.  The panel discussion is on the business of the Smart Power Grid, and which sides of it have the best opportunities and jobs.  Speakers from the event include Marvell which will be discussing the use of connected embedded controller devices in a proactive role for monitoring of energy consuming products in the home.

In addition to industry speakers, several industry renown consultants and academia personnel will be presenting trends and innovation talks and challenges for the industry.

For information and registration please refer to the conference web site www.spgtc.org

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At the SPIE Advanced Lithography event in San Jose, Synopsys presented their current mask making solutions.  The solutions include : (A) Proteus Litho tool (OPC & LRC) for mask synthesis, (B) CATS for mask write, fracture, inspection and metrology,( C) Sentaurus for process and device TCAD, (D) Yield Expolrer/Odyssey which is a design centric yield managment tool and (E) LightTools/CodeV for optical design and analysis.  At the litho event the concentration was on the Proteus tools and the link between stages.

The delays in EUV have forced the current litho equipment to push past the 28nm node to the 20nm production nodes with the use of complex techniques such as double, triple and quad patterning.   The first use of limtited funtion EUV is now targeted for the 16/15nm node and wil require new corrections alogorithms and run time solutions.  For EUV one of the major changes is the writing of full reticles not jsut single fiels.  This changes the methodology and strategies for RETs such as DPT and MBAF (model based assist features) and how thet are put into the design.  At 16/nm the RET sequnce will include RBOPC, MBP{C, RBAF, SMO, MBAF, LELE, IMT, Spacer, LRE, and MEC for a supplement to the ArF Wet/EUV/eBDW litho flow.

The Proteus double patterning tool (DPT) solution delivers a design based compliance solutions to avoid zero yield masks, a cost based solver to minimize pinching and bridging, symmetry enforcement for better runtime and color balancing for uniformity between the two masks.  These solutions are part of a full flow for design that includes DPT awareness in placement, routing, compliance checking and fixing, creation of compliant GDSII, and DPT compliant fracture.

A major new feature of Proteus is the support Long Range Effect (LRE) for use with EUV.  These include mask shadow modeling and 3D compact models for improved accuracy and tunable short range flare parameters.  These models and the tool runs on standard x86 hardware and support pipelining on all steps. The prodcuts are currently available.

March 15, 2011 – Santa Clara, CA – The 12th annual ISQED conference (www.isqed.org) kicked off with the themes of next generation systems and applications.  The keynote “Multitechnology Hyperintegration Platform: the technology crystal ball” by Dr. Kamran Eshraghian was very engaging and well received by the early morning audience.  His discussion focused on the creation of disruptive technologies based on the SoS or System on System space.  The innovation gestation period was shown by example to be about 30-50years from creation of the concept.  This was illustrated under the timeline for the Memristor – it was theorized in 1971 and then realized in 2008, its manufacturability and integration into products is still on-going and is expeced to hit its peak in the 2020′s.

On a similar schedule, the new area of amibient intelligence – or pervasive computing and connectivity was launched in 1987 and should see initial realization in 2020, with production in 2030′s.  Another area of discussion was the creation and use of metamaterials.  These are materials with non-standard characteristics since as a negative k factor for optics.  These materials, as well as the continuing shrinking of micro designs to nano designs, will result in new interactive systems and sensors that will be largly photonic based.  Dr. Eshraghian discussed how we currently don’t have a crystal ball to show how these pieces come together, but the direction is that the technology, once mature, does make its way into the nominal consumer culture on a global basis.

On the following technology progress line, the next speaker was Dr. Fabian Pease.  His topic of discussion was “For how much longer can Moore’s Law hold?”.  His discussion focused on the actual drivers from the current technology node, and made the argument it is NOT the transistors, it is the wiring that is in the scaling equation.  The key to Moore’s law is the lithography scaling in both geometry and cost.  The 500x increase in the cost of the litho equipment is directly proportional to the 500x decrease in the cost of minimum sized devices in the process.  To make the next transistion, something radical has to happen.

In his discussion, he indicated the most significant advance in process technology since the start of the CMOS era, is the application and development of Chemical Mechanical Polishing (CMP).    The next area of development to help maintain the density scaling is to move away from the confinement of a single plane technology.  3D technology and multi-technology stacking will help push the scaling for another several decades and will help remove the direct cost proportionality with the cost of litho. In the 3D world, the mixed technology allows for functions  to be implemented with both high and low litho cost processes, that can meet the scaling rules for functionality and not exceed the cost constraints that are needed for high volume use.

The second day of the conference, Robert Patti of Tezzaron Semiconductor, gave an overview of 3D stacking technology, and their wafer bonding technology.  The method they have developed and licensed to many major semiconductor companies, is based on face to face landing pad bonding of two designs – typically processors to memory, and can contain billions of vertical connections per 300mm wafer.  The discussed the reliability of the bonds, and that thier methodology requires the application to create the test methodology based on post assembly test.  They do not run tested die on the wafer, as it introduces mechanical damage to the wafers,, instead they rely on PCM tested wafers.

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