Apr 24 2012

Intel 22nm production for 13 processors

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On April 23, 2012 Intel introduced their new Ivy Bridge Core processors for the desktop, All In One (AIO) and traditional laptop marketplace. Based on the challenges that most of the semiconductor industry has been having with manufacturing below 40nm, the key technology piece of the announcement was the 13 processors, including the 3 un-locked processors which allow over-clocking, were being released on the 22nm Tri-gate process.

This is the first major 3D transistor product launch in the industry and represents a 2-3 process generation (32nm, 28nm planar and now 22nm tri-gate) advance over most other semiconductor fabs. The devices, being patterned with immersion litho and multi-patterning, are able to yield at acceptable levels for world-wide launch of the processors next week.

The performance advantages of the 22nm Tri-Gate process provided capabilities in realization that were not part of the original expectation, which allows them to move to a “Tick+” step in their “Tick-Tock” process/architecture progression. The new process also allows them to implement these new processors in a new format PC that of the AIO. This segment seems to be growing as the power/performance curve brought on by the new process is rolled out.

Mark Bohr of Intel discussed in the Q&A portion, that with the release of the 22nm process, that activity was progressing on the next gen 14nm and 10nm processes. These would also be Tri-gate 3D device processes and while it would be good if EUV was available, they are moving forward with the schedule for roll-out of of the processes independent of the availability of EUV for production.


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Mar 09 2012

ISQED2012 Expands with Co-located Events

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The 2012 ISQED (International Symposium on Quality Electronic Design) is expanding this year to include two co-located events at the Techmart in Santa Clara on Monday 3/19 and Wed 3/21 of the three day conference. While the main program has continued to focus on the the quality of design in both the systems and process space, it is increasingly covering tools, IP blocks, SOCs and full electronic systems. There is a migration of topics to include process and manufacturing interactions with the electronics. .

The conference schedule includes multiple sessions on power aware design, energy efficient design, 3D packaging and analysis, and system level failure & test methods. The plenary talks by Cadence, GlobalFoundries and UCSD focus on advanced node processing & design, IMEC is speaking on Variability, Aix-Marseille Univ on the topic of Resistive Memories and Texas Instrument son the topic of Analog Innovation. Synopsys will be presenting a retrospective talk on the trends on the collaboration between the Space Program and the electronics industry.

The co-located events are covering the expanding ecosystem of the system design community – education and sensors. They are the Interdisciplinary Engineering Design Education Conference (IEDEC), now in its second year, and SensorsCon. Engineering education has to change from the traditional non-interacting silos to be able to take advantage of skills in multiple programs to solve current and emerging problems. With this concept in mind, the IEDEC event, being held Monday 3/19, is focused on multi-skill and multi-subject course work that better fits todays engineering realities. It discusses coursework, programs and curricula for crossing the traditional engineering school vertical tracks. The program is highlighted with presentations from AMD on hardware/software co-design with OpenCL, TE Connectivity on incorporation of hardware/software/social engineering and data mining for digital signage, CSNE Albany on the creation of an ABET approved Nanotechnology degree program, and UCBerkeley’s CITRIS program on the role of Computing on Interdisciplinary Data.

SensorsCon was developed to address the rise of the Internet of Things (IOT). IOT and mobile devices have brought Sensors to the forefront of the electronic system universe. The event is being held Wed 3/21 at Techmart and addresses the non-standard devices, that brings a number of challenges and reliability issues to the system design arena. Industry MEMS pioneer Janusz Bryzek from, Fairchild Semiconductor, Bosch, Intel, Dust Networks, Sensors Platforms, Sprint, Mphasis, California Polytech and Microlytica, will be presenting on the manufacturing, design and implementation of building high reliability consumer and industrial products that incorporate a Sensor base.

Registration for all conferences, being held at TechMart in Santa Clara,CA, is open now.



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Mar 01 2012

DRAM updates at ISSCC 2012

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At the recent ISSCC, the DRAM rollouts took place opposite of the microprocessor announcements. The well attended session was greeted with several themes – new interface and performance, lower power, higher densities, and new processes.

The new 3.5Gbps DDR4 SDRAMs were introduced by Samsung. Not only is the interface faster, but it brings new levels of error correction and tolerance through an improved signaling method. Hynix also introduced a DDR4 SDRAM product that uses the lower 1.2v operating voltage, a x4 half page architecture and a reduced active bank current. These devices again not only focused on the speeds possible with the new interface, but the improved reliability and data integrity possible.

As these devices move through process technologies from 38nm through 20nm, device and signally reliabilty with the lower operating voltage was the driver. Architecture changes, sense amp, cell and read/write cycle changes have to be implemented to support the needs of the 1.2v power supply for high speed server memory. For mobile applications, the speed is not as critical as the power and the reliabliy. UCLA presented a mobile memory interface with a power factor of 4pJ/pin that supports a 5Gbps BaseBand and 3Gbps RF band data rate while maintainng a BER of 10-12.

The session then moved to process technologies. Higher densities and performance were achieved with TSVs as a method for addressing leakage current for power reduction. In addition to TSVs, new memory technoligies in the form of Phase Change were shown. Samsung displated a 20nm 8Gb PRAM that operates at 1.8v and was able to support a 40Mb/s write throughput. This was a significant density, performance and power improvement of prior work.

These papers represent the shift in enterprise and mobile DRAM from density as the key driver to power and reliability as the #1 and #2 application targets. Just like processors, there is more the memory market than cheaper/higher density, making sure they work is now the key.

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Feb 19 2012

eBeam and EUV move forward – Adv Litho 2012

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At the 2012 SPIE Advanced Litho Conference the show floor was not very crowded, but the sessions were overflowing – literally. In all the sessions I attended – EUV, DUV, Self Assembly, multi-patterning, not only were the rooms standing room only with all the walls covered with attendees that did not fit in the allocated chairs, but most had crowds in the video relay overflow rooms.

The eBeam initiative along with D2S presented an update that showed progress from multiple partners including a presentation by IP partner Tela innovations in cooperation with CEA-Leti. This work was based on their 1D device topologies with a circular spot in the alternate axis to do pattern definition. This methodology was shown in detail at the conference on a paper based on their 11nm findings. This work expanded on the concept of shifting the VSB and now circular beam spot shape to being used for mask creation and result in a high CD uniformity (CDU) than traditional approaches.

While the Direct write methodology is still being pursued, (enhancements possible with new tools such as the Mapper high beam count cluster tool) the throughput does not compare with the use of the tools to create a traditional litho mask and then process the wafers as normal. The direct write on wafer methodology is still being reserved for key MPW prototype work. Both the mask and wafer direct write flows are moving ot a model based data prep and incorporating circular and character shaped beam images.

The discussion on EUV showed that the technology is making great strides. The power for EUV systems is on a path towards practical use in 2012 which is on track for 2013/2014 production levels. Several papers were presented on the duty cycle, cleaning models, beam purity and other details that well beyond the “we have an idea to try” papers that were common in the sessions in the past.

Gigaphoton have an EUV update shortly after celebrating their shipment of their 1000th laser system. 2012 will have thier EUV system shipping in addition to thier DUV solutions. They are releasing a 7w clean power sytsem based on a 90khz Sn droplet rate EUV source to ASML this year. This 7w core is bign ganged and increased to 50W by Q4 fo 2012. The 50W clean power unit can be ganged to produce a 250w 100wafer/hr system by ASML.

At this time, the system is running an 3.8% conversion efficiency at 2.5mJ at a 10hz droplet rate, This directly scales to 250w at at 100kHz droplet rate. The challenge is the on-demand droplet generator using a 20u Sn droplet.

On the DUV side, Gigaphoton had improvements in both eith KrF and ArF systems. As a focus on manufacturing vs cost of ownership (they use a cost per pulse billing model that is full service rather than a putchase/supply model) their improvements are related to total system throughput and downtime. One of the major advancements was the creation of a new STGM sensor for the ArF lasers. The new system has sensors that monitor Oxygen in the system rather than the Argon and allow the progress to be monitored without a loss of ArF gas and the downtime to return the system to a low vacuum level.

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Jan 16 2012

Interfaces dominate CES IP

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At the 2012 CES conference, there were many IP providers mixed in amongst the many end product companies. These IP providers were showing capabilities as a well as ASSP products targeting the mobile community and handheld products.

The core controller IP providers – Tensilica, ARM, Imagination Technologies and MIPS were all showing their latest scalable blocks targeting higher performance graphics, sound and battery lifetime. These blocks were supported not only be new SDKs but also in reference designs that appeared as early product from the major systems providers.

A change this year was the large number of IP blocks that were incorporated in ASSPs that were shown. Companies such as Nvidia, Broadcom, Samsung, Qualcomm and Marvell were showing thier own versions of these IP blocks, now configured as systems under the larger scope of an architectural licence for these core processors.

Peripherals and interfaces were not left out at the show. The Qi group (Wireless Power Consortium), USB IF, WiSA and Wireless HD, HDMI and Display Port groups had multiple vendors showing both IP and systems/block level solutions. The data rates moved up at the show and most people had the new standards – SATA 3 (6Gbps), USB 3.0 (5Gbps), Thunderbolt (up to 10Gpbs), Display Port 1.3 (5Gbps) in thier products. This has changed the technology node to being 90nm as the largest process size, as the SERDES at this node and below can handle the high speed data in a straight forward manner.

A couple of surprises in the IP is the large number of blocks that stayed at the 1.8v power rails, and did not scale to 1.3v or below. While beneficial for the core logic and state machine portion of the design, the power level has proven to be quite challenging to interface blocks and anything driving large capacitive loads such as cables or connectors.

The FPGA providers were focusing their IP and solutions on the high end display (multiple TV models) and the automotive marketplace. These are both aggregation points for multiple technologies and multiple data bus formats. As a result, the flexibility of the FPGAs logic to be adjusted on a per model basis while providing sub 3Xnm process and performance access is the major driver for the UHD displays and advanced Driver Assist and Automotive Infortainment systems that were shown.

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Dec 27 2011

IEDM 2011 – EDA shifts to TCAD

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At the IEDM conference in Washington DC this year, the electron device conference moved up from basic layer and element creation for sub 20nm processes and new device technologies. The past couple of years, the conference focused on the ability to create these devices – 3D transistors, FinFets, Graphene devices, double and quad patterned memories – all as can we manufacture them.

This year, the ability to make these devices was second to how do the devices work, how should they be modeled to be compatible with the design community and what are the sensitivities and variability associated with the parametric performance of these devices. The processing capabilities have improved to the point, where these technologies can now be built at production scale for the semiconductor industry. The big question is – can designs be created that can simultaneously take advantage of their new performance characteristics while compensating for the challenges of these devices and their differences from the traditional MOS switch?

To address this question, about 30% of the sessions were focused on the device modeling and the actual current transport mechanism in the new structures. These included, the associated variability in gain, on/off resistance, and the transconductance and other basic device parameters. These were both shown from empirical data collected and from TCAD and mathematical models. These models were used, and shown in the joint circuit design session, as part of the advanced applications sessions.

The models were not just for single devices, but there were tutorials and findings on MEMS, Sensors, Biodevices, Energy Harvesting Devices, and high power (up to 6.5Kv and 2500A) solid state transistors also. These technologies, more so than traditional lithographic scaling, are becoming the new drivers for advanced technologies. The capabilities of the solid state devices has now moved on from just smaller/faster to being new capabilities, power aware and context aware.

As a result, the understanding of how these mechanical and biological interface devices as well as power handing devices – all of which are not handled by traditional RTL and digital verilog descriptions – will be the new basis for broad appeal design moving forward. The EDA community has not really been addressing this as yet, as it is not algorithmically derivative of current solutions tools in the market. These new markets are currently being addressed by TCAD tools, mathematical and physics based modeling tools and in-house created tools as has long been the mainstay of the analog/specialty design marketplace. As things move forward, the mainstream EDA community has to address these directions and bring solutions or the in-house ad-hoc solutions that are built for a specific process will once again dominate the design industry as it did in the 60′s-70′s pre-EDA gen 1.

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Nov 26 2011

ARM Mali T658 Graphics CoreARM Mali T658 Graphics Core

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ARM just introduced a new high performance, low power, graphics core that can be instanced as multicore for up to eight instances as a GPU in the Midgard architecture for sub 32nm process. The Midgard architecture now has the T604 and T658 as multi-core visual computing cores. The two main features of the new core are the ability to scale to 8 shader and arithmetic pipes in one core and an extensive API library that allows for commonality of code across multiple platforms (mobile to large screen TV).

ARM Mali T658 GPU Architecure

The multi-core architecture required a new cache system to provide increased coherency for the 8 cores. They are grouped as a single cache shared with 4 shader cores sharing a memory management unit and an AMBA interface. The core now supports an integrated automatic load balancer for the cores. The target mobile applications is superphones in either a quad or octal configuration with the “big-little” CPU cores the Cortex-A15/A7 pairing.

The shader set supports graphics APIs – Direct X10 & X11, OpenGL, OpenVG and computer APIs – OpenCL, Renderscript and DirectCompute. The APIs have already been incorporated in to several development systems including the game development tools from Unity.

As the IP block is targeted for implementation in licensee SOCs, multi-stream data access, incorporation and support of a hypervisor, vitalization of the memory access and multi-display drive are currently not part of the IP block, but are being developed the partners in the ARM ecosystems for vertical market specific needs.


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Nov 08 2011

Update on Nano-Photonics

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The IEEE Nanotechnology Council is holding a half day seminar on photonics on Tues Nov 15 in Santa Clara. (info at http://www.ieee.org.nano) The area of photonics is quite varied these days and the program is addressing 4 key areas of the technology.

Opening speaker Dr. Hughes Matras from CEA Leti (Grenoble, FR) will be discussing 3D ICs and chip-to-chip photonics interconnects. They will be presenting results and goals for thier ongoing research in the space. These parts are targeted for both Si based photonic circuits – logic to logic and logic to memory.

The second speaker is Dr. Chanming Su of Bruker-Nano. Dr. Su has create a fast scan Atomic Force Microscope which now enables single digit nanometer resolution metrology at practical quality assurance and debug speeds. One of the major challenges of nanotechnology is the imaging of the geometries in question. A second challenge is to verify that these sub-resolution features and the resulting devices are created properly. The presentation will review the technology behind the Fast Scan AFM as well as capabilities of the tool in production use.

The next speaker will be Dr. Hakaru Mizoguchi of Gigaphoton. He will be discussion the advances in EVU lithography through their development of a new high power EUV source. The new source is based on an ionization system for the liquid Sn droplet atomizier. The final speaker is Dr. Xiang Zhang of UCB. He will be presenting on solid state lasers and limits on diffraction grading and other optical elements in solid state light paths. These products are a critical part of high speed communication.

After the speakers presentation, Ed Sperling of Semiconductor Manufacturing & Design (www.semimd.com) will lead the panelists in a discussion of future directions and challenges in integrated photonics and the process technologies they will be using. Registration for the event is available on-line at www.ieee.org/nano and admission is also available at the door for the event. The event is being held at the Texas Instruments Conference Center in Santa Clara. The center was formally the National Semiconductor Conference Center and runs from 12noon – 5pm on 11/15. Lunch is included and parking is free.

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Oct 29 2011

ARM Highlights Power and Processors

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The 2011 ARM Techcon was well attended and busy this year. The technical sessions were rightfully quite packed as the topics being presented by ARM and it is many partners was low on product advertising and high on technical content – a rarity for many of today’s events. The conference addresses a diverse client base – IP creators/providers, SOC developers, FPGA users that integrate the cores, and systems designers that use both custom and standard products that incorporate the ARM cores. In past years, the communities were tightly integrated, this years event, chose to separate the two groups (chips and systems) segregating the “chip” folks to the “kids table and being out of sight/sound of the adults” and the “systems” folks to the “grown ups” who got the “big table in the main room”.

The challenge that results, is that attendees who are doing SOC design for a specific application, now need to attend all three days, but two of the days do not discuss the context of the architecture, test, programming and performance optimization that reviewed on the Systems days, The attendees building systems now also have to attend all three days to get the technology overviews, low power techniques, reliability and interface details from the chip day to understand how to take advantage of these features in their FPGA and board level implementations.

There were a number of design tradeoff sessions that had new design solutions such as the SiTime MEMS resonator which in addition to being a stacked die integratable solution, also allows for the elimination of PLLs in the SOC design and the timing issues associated with the jitter in traditional PLL based clock distribution designs. This is becoming more critical as additional sensors are being used in these multi-core systems, so temperature compensation and data converter stability have increased impact on the overall performance. The results are fsec jitter levels on a 100Mhz clock.

The systems day included an overview of ARM itself and had a nice tradeoff comparison of the ARM vs Cortex processors, and the 16, 32 and 64 bit instruction sets, applications, and programing requirements for the various applications. This discussion included the multi-core architectures and pipeline designs of these cores and the associated AMBA system IP / Mali Media IP.

An overall theme was that the ARM IP was designed for minimizing power consumption while providing the highest performance/power ratio in the industry. This has allowed the IP to be used in literally Billions of end products shipped, since the company was formed in 1990. The product line was shown to be addressing the shift in market need from simple control of an application to being a main compute processor for mobile multi-media data consumption.


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Oct 21 2011

Power Architecture turns 20

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In a recent discussion with Fawzi Behmann, we reviewed the state of the Power Architecture, which is now in its 20th year. The processor was started as reasearch in 1977, and then became a a standalone product (the 68000 processor) in 1979. The Power Architecture was put into SoCs in the early 1990′s and was introduced as a multicore with virtualization architecture in 2001. The current version of the processor – the Power7 is the compute engine behind the IBM Power7-Blue Water HPC and the Blue Gene / Q. The group Power.org put together the Power ISA in 2005 that created a spec for the product and specified the supply chain. In 2010, they released version 2.06B of the spec, which dealt with multicore, virtualization, energy management and reliability of the design and cores. The core is now able to take advantage of new operating systems and appellations thanks to new SDKs that have been developed. They are moving to run OpenCL and Android has been ported to PowerPC along with the other platforms. This allows for embedded applications to get an optimized OS, and the code is available in source form, and proprietary kernals can be developed. The graphic that follows shows the current roadmap for processors and cores.

Power Architecture Roadmap

One of the new applications of the part which has dominated space use, medical instruments and automotive, telecom, compute/analytic applications is natural language processing. This is not the same as the regular expression processing for policy decisions, rather, it is targeted at health care and medical record processing. The engine can process upwards of 200M pages/sec of EHR. These new applications are starting to take advantage of the transactional memory design in the Power7 which is optimized for multi-core processing. The SoC design for the cores is a hardware/software co-design function. The designs are captured using Rational. And then a flow (as shown in the following figure) is used to create the design using EDA tools from Synopsys, Cadence and Mentor for the hardware design. The design is a true 64 bit with full 32 bit subsets.

Hardware/Software Collaborative Development

To enable new development and increase embedded applications, Power.org has worked to simplify the licensing of the technology. The license model now includes: IBM Power Architecture Licensing Program – Lowering Barrier for Developers (a) “No-barriers” license for Power 405 (no standard access fee) (b) Multi-use agreement for Power 405, 460 and 470 for 5-years (c) Synopsys University program for Power 405 member access for new applications (d) VAR agreement with C*Core. These licenses have additional provisions for China and as a result they are experiencing high growth in multiple markets.

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