The lead off question for the event was, “Why an Innovation Summit?”  The consensus from the organizers was that we are currently in a down market, there is no coordinated government support for innovation, there is a large slow down in IPOs, there is currently a poor innovation infrastructure and most emerging markets have a lack of understanding of science and technology’s role in innovation.  This lead to the following preface to the keynote speakers: For innovation to be a successful, is it the invention, the business model or both?

There were three keynote speakers - Henry Chesbrough from Berkeley, Robert Byer from Stanford, and author Dr. John Kao.  Mr. Chesbrough’s keynotes focused on the shift from the current closed innovation system to an open system.  This closed system is the idea of multiple research topics being reviewed and the development being selected as what best supports current and historical business models.  The open systems has multiple research topics being reviewed and results in both development being selected for the existing revenue stream as well as development supporting adjacent areas through technology licencing and royalties, creation of spinoffs and valuing IP in both a fully realized and staged mode.   The reasons behind this shift included the increasing mobilization of resources and the enormous increase in venture capital.  The conclusion was these innovation models were built jointly with business models that creates value for the customers and allows the owner of the model and innovation to profit from the creation.

Robert Byers presented a historical perspective on the “silicon valley” model and the close relationship between universities and corporate development.  This included the historical interactions between Stanford University and Hewlett Packard Corp as well as the creation of PARC and SRI.  The importance of the university knowledge base for basic research and education was detailed as a key for enabling commercial innovation.

John Kao presented some of the concepts from his book “Innovation Nation”.  These concepts
included the global basis of innovation, and the what, why and how of innovation.  The what was described as creativity for a purpose that applies a value.  The why is based on the 3 pieces of innovation - talent, capital and ideas.  The how is compsoed of two concepts - (a) having a defined vision that includes a sense of urgency to address it and is measurable and (b) there is a responsible steward for the vision.

The afternoon sessions were high level strategic direction discussions about new technologies being created in the areas of solar, lighting and biophotonics.   These were introductions to topics of short term and long term development and the divers for these innovations.

As a kick-off event in a marketplace where even established events are having trouble with attendance and quality of content, this was a very strong event and if the organizers continue to attract the same high quality of presenters, then the event will continue to be well received and very beneficial to the technology and optics community.

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The morning had two keynote speakers, Design-to-Silicon VP Joe Sawicki from Mentor and Chad Hawkinson VP of Vertical Market Strategy from PTC discussing a joint program and direction with Mentor.   Joe’s Design-to-Silicon group covers the new combo of Olympic SOC, the Calibre franchise and the Test Kompress products.  As a different spin on the technology pitch, the discussion was nicely high level and was an overview of some of the design/build information from the SOC implementation perspective and how tools address the whole life cycle of the product creation through production release.

The presentation was thankfully short on the standard DFM SEM photos, the obligatory “random defect” photo that has been shown since the late 70’s and the Litho related “contour” plots.  The presentation, however, did show a strength for Mentor of understanding the IT impact of the current process technology and their approach to tackling the issues.  As the process technologies scale down, the amount of content in the designs (geometries, firmware, gates, layers of interconnect, manufacturing/lithography steps involved) does not scale linearly.  As a result, the new designs require several orders of magnitude more data to be processed in an ever shortening product development cycle.  Mentor has addressed this with aggressive adoption of multi-core, multi-thread and distributed processing for their tools.  The methodology includes true scaling from single CPU (multi-core) environments to full cloud computing environments to best optimize through put for design at the IP to SOC level.

The new optimization message for the 45nm and below era is now targeted at workflow optimization as is seen in data reduction, Multi-Corner Multi-Mode (MCMM) analysis, Multi-core Multi-threaded computer environments and the understanding of both technical drivers and business context as parts of the current design flow. The new workflow includes the Olympus SOC product as the central evaluation engine for the variability and power design / analysis issues, the incorporation of CAA (Critical Area Analysis), LFD (Litho Friendly Design) and CMP (Planarity modeling) into the DFM tools and the addition of Yield learning to t the Test Kompress production test environment. This keynote acted as a lead-in to the Calibre DFM roadmap held later that same day.

The second keynote addressed the larger system aspect of the Mentor product offerings.  It was presented by PTC and discussed the combined workflow of the PTC MCAD (Mechanical CAD) & PLM products and the Mentor ECAD (Electrical CAD) tools for PCB and system firmware.    The new system environment includes interaction in component & board design, revision control, user software/firmware and industrial design aspects of a product development program.  The keynote represents one of several partnerships in development at Mentor on the path of component, software, RCS and PLM space.  One of the keys in he integration is verification and validation of the design

Mentor also presented thier Calibre DFM roadmap that afternoon.    The discussion focused on the new members of the Calbre family - Calibre YA (Yield Analyzer), Calibre LFD (Litho Friendly Design), Calibre YE (Yield Enhancer with Smart Fill Technology) and Calibre CMPA (CMP Planarization Analyzer).

The YA product is an integration of the prior Mentor CAA product with the tools that were brought in from the Ponte acquistion.    The product is incorporated into the RVE debug environment and has support for both library characterization level and the full chip level.

The LFD product incorporates variability analysis and identifies design robustness that helps minimize litho related fallout.  One of the major enhancements is the ability to perform this analysis in a time scale that is applicable to use in a normal design cycle.  Prior generations of tools from vendors in the EDA space, were not capable of producing this level of quality of results in a cycle time that could actually be used as part of a design flow.  These enhancements are partially responsible, in addition ot partnering arrangments, to the approval of the tool in the new TSMC Version 9 reference flow.

The CMPA and YE tools are related to both density and litho aspects of the interconnect fill.  The YE product uses a new algorithm for planarization fill called SmartFill.  This not only operates in 40-50% of the runtime of prior traditional dummy fill techniques but is 3D aware and supports non-rectangular fill so that performance of the fill is optimized.  The CMPA tool incorporates features of the new eqDRC capability to allow for equation based descriptions of the design rules.  As these features are depth of field sensitive, the tool targets and minimizes overfilling with “dummy metal”.

Future directions include Reduced Design Rules (RDR) Physical Verification (PV) that is grid oriented and context awareness for rules.

As a change from the traditional PV direction at the User Group Meetings, the Calbre and Design to Silicon platform were finally messaging the whole flow of the tools from design entry, physical design, verification and test rather than a series of point tools that the customer has to integrate themselves.  The support and service model as well as design interoperability that hte customers have been asking about and that they have been presenting results on for years.  It is good to see the direction acknowledged and finally moving Mentor from a point to provider to being a solution provider.

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The sector has been self-victimized by the same sort “creative” accounting practices that plagued the dot.bomb craze and the current energy/real estate debacles along with an overall lack of cohesion for a common purpose.  This has resulted in the EDA sector having difficulty justifying making growth, realistic booking goals, a consistent definition of what industries make up the segment and the admission that the cost of development of electronic products (the end customer marketplace) has resulted in a dwindling number of customers that can afford their products.  Cadence being one of the bigger players in the field and promoting the house of cards, is just having an implosion at the leading edge.

What is interesting about the industry and the current situation at Cadence, Synopsys, Mentor and Magma is that the technology they have is actually quite sound and innovative.  To make a very gross high level generalization - Cadence and Magma are having problems with the financial community due to validation and forecast of booking and long term revenue based on not showing the global reduction in design starts, Synopsys and Mentor are getting beat up in the market because they are projecting conservative verifiable estimates which shows slow/no growth in a declining economy.  Translation - if you push the numbers, they street dumps you, if you play the numbers close, the street crucifies you - either way EDA as a sector has a problem.

The recent management at Cadence seemed to be operating under the assumption that their products were simply shrink-wrappable components that could be sold to anyone with the money to buy them.  They also followed the standard product/stocking distributor/retailer premise that new products are at a premium and you heavily discount to clear old products from inventory.  Unfortunately, EDA is a long life cycle business where the maintenance and service revenue from these older products (i.e. simulation tools, custom design, pcb) account for significant portions of the base revenue stream.  These sort of decisions are being made by multiple companies who still believe that EDA is a valid standalone sector.  The reality is that the EDA biz unit came from the electronics supply chain for a full system product life cycle program, and that breakout of “component design creation” as a parallel sector is reaching maturity and the interaction/integration of the tools, planning and manufacturing has to be re-integrated into the product cycle.

So where are we - you have a couple of big boats in the water, without a destination for where they are headed, one does not even have anyone steering the ship.  You have a couple of big boats staying in the middle of the river, heading slowiy upstream and betting that things are better there, but being careful to not crash the boat.  The rest of the private guys are just blinding following in the wakes of these boats, hoping to be acquired and brought on board, even getting on board with the directionless boats.  It would seem, the best bet is it to stop the drifting, nuke the directionaless boats and send the people out on life rafts to new industries, and redirect the two good boats to the semiconductor component and equipment channels where there is at least a positive TAM still available.

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The technology is targeted as allowing for the identification, selection and modeling of both standard illumination patterns (quad, dipole, etc) as well as custom patterns available with off-axis illumination.  The result should be design optimized illumination that is hierarchically constructed to support a single optimized illumination pattern for the whole reticle area.  Similarly to the Mentor/IBM announcement, there are no production lithography tools currently using programable illuminations sources that can use this technology.  Where the Mentor solution is targeting masking and fabrication partners for the development of the technology, Cadence is moving one step earlier in the life cycle by partnering with a component supplier who may be selected as part of the stepper manufacturer’s equipment.

The technique is not targeted at just 22nm, rather it is a generalized approach that can address all sub-wavelength technologies.  The advancement of the technology should result in a more usable set of “working design rules’ rather than the complex group-by-group decisions on required rules, optional rules and suggested rules currently presented by the wafer fabs.

The solution is part of the Cadence Process and Proximity Compensation (PPC) technolgy offering.  It supports bith single and double patterning solutions, is targeted at high throughput and features enhanced rapid design convergence (single digit iterations).  Cadence/Tessera’s simulation have shown that the use of these techniques results in an improvement in process window yield.

As in the other releases in the SMO arena, it is a watch and see technology to determine if (A) the equipment manufacturers can support/adopt such a technology without impacting throughput and reliability, (B) if the fabs and processes can provide support for this additional level of variability to the deign community and most importantly ( C) if the cost of implementing the technology and its associated simulation/IT infrastructure requirements can justify the return on yield for end semiconductor products.

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The premise is that the serial timing closure (timing analysis, goal identification, design re-optimization and then multiple iterations) gets excessively long in 65nm and below processes due to the large variety of corners, modes and design optimization techniques available.  The Olympus engine inherently addresses the problem of the MCMM space by creating “solution scenarios” for the engine to solve.  These are a space consisting of simulation states like Power1-Corner1-Control_state1, Power1-Corner2-Control_state1, Power2-Corner1-Control_state2, etc.  The new enhancement is for making the timing closeure portion a SMP (Single Memory Parallelization) application for multi-core, multi-thread processors.  This allows these multiple simulation states to be solved simultaneously with adjacent cores.  As there is already a set-up engine for these tasks in Olympus-SOC, the resulting overhead is just on job launch and results gathering.  This allows the performance to be at 7X for an 8 core (dual quad-core processors) machine.

Mentor has taken this a bit further than just timing closure, to includes design closure.  The optimization loop includes validation and auto-selection of options such as gate sizing, buffer insertion, path duplication, and logic re-synthesis in order to achieve the timing specification required.  As the environment is a physically aware system, SI, EM, IR Drop, and OPC/RET issues are also part of the constraint space for design closure.  They use these optimization techniques in addition to the MCMM environment, to identify a solution that meets the timing requirement or indicates that constraints cannot be met.

The automated selection of solutions for the traditional timing closure, including SI, EM, etc, has a known history of acceptance within the design community.  The extension to the MCMM decision space may also be accepted in the design community, provided there is traceability to the decision path that was used to find the solution.  In these two cases, the decision on “meets the criteria or not” is a fairly binary yes/no decision.

The paradigm shift that is being presented is not really the adoption of parallel processing to the timing closure task, nor is it the further applicability of the physical awareness to parallel processing.  It is primarily the automated selection of design closure alternatives in context of the physical views.  As these design optimization solutions have both structural and functional characteristics, the selection of the solution method has traditionally been steered by the designer based on the review of available solutions that are presented.  For a large number of the cases, the involvement of the designer to select the tradeoffs in  the structural  design is not required, as there are usually one leading solution to the design space.  The main question as a result of the product release, is if the design community will embrace the automated selection of solutions for the entire design space, and how much manual intervention is supported and easily allowed.  If the product is architected correctly, as Mentor is claiming and is being proclaimed in the customer testimonials, then the market will see a big winner and a paradigm shift, otherwise, it is just another one.

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The IBM facility is a current 140,000 sq. ft, approx 4000 wafer/week 300mm facility with an in progress of being configured 72,000 sq. ft annex.  The main fab floor is for 130nm, 90nm, and 65nm production at this time.  The annex is in phase 1 at this time and is supporting a mix of 65nm/45nm production and 45nm/32nm process development in approx 40,000 sq. ft.  Phase 2 will be the balance of 32,000 sq ft and be targeted for 32nm manufacturing and 22nm development.    Process and lithography development down to the 15nm node is being done at their partner facility the College of Nanoscale Science and Engineering at the University of Albany.

The new method is based on expanding some technical and business concepts: (1) computational lithography (CL) which incorporating a manufacturing tool control called Source Mask Optimization (SMO) with Mentor Graphics and Toppan Photomask; (2) exploring development options and strategies through a TCAD based virtual fab in conjunction with Rensselaer Polytechnic Institute (RPI) and (3) design technology co-optimization that is identifying directly measurable manufacturing rules and techniques as a joint effort between Mentor and IBM.

The CL portion is an extension of the existing DFM flow which has focused on just physical design database adjustments using OPC and other traditional MDP products.  Mentor has already demonstrated the expansion of their Calibre products to support distributed. multi-threaded, multi-core and other high capacity compute environments.  The advanced development work with IBM will include fundamental research on applications with GPUs, the IBM Cell BE processor, and other engines that may be used in a “cloud computing” or “supercomputer” environment.  The need for this is to provide rapid turnaround on the complex problem solving for the new imaging simulations.  The main ideal of the new CL was to develop a method of providing lithographic solutions for specific areas of the chip being processed fast enough to be usable on the factory floor.

This manufacturing floor solution would be coupled with in development, but yet to be available 22nm masking equipment, that can use a programmable or variable light source.  Current masking equipment uses fixed illumination sources for an entire reticle area.  The added flexibility of SMO would allow for function specific and portions of the reticle (e.g. memory cores, control logic, high speed paths) to not only be optimized with traditional DFM tools, but also add the new dimension of source style (single point, dipole, quad, etc) in order to allow for imaging the 22nm process.  This SMO will reduce the high amount of complexity of the data on the mask, and shift some of the complexity to the masking equipment and the light source.  The impact will now be both mask and source simulation data processing.  Toppan Photomask is participating in this portion of the program to help incorporate constraints on the reticle preparation, use and defect inspection & repair.

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In recent discussions with Jabil, they have refined their model and are expanding in two areas - localized supply chain implementation and semiconductor supply chain.  The driving forces for this refinement is minimizing the cost and time associated with the logistics of material movement from component production to test to system assembly.  In the medial and instrumentation space, the localized supply chain has focused on supporting and supplying ROHS compliant services and facilities as a migration path for their customers.  This approach is being targeted at a global expansion model after strong success in North America, solid migration into the European community and early phase in Asia and the Pacific Rim.

The need for this model is to support the increasing diversity of low & mid volume high product mix applications.  These applications need a supply chain that not only includes standard subcontract manufacturing of the boards, component assembly and insertion into enclosure but also includes incomming component screening, in-production test, post-programing test, final test and packaging insertion.  At this time they are operating/supporting 14 factories worldwide.  On the medical side products include: digital imaging, patient monitoring, record keeping and patient bedside PCs and connected display environments, and in-hospital flatscreen/portable products.

The transition to the semiconductor supply chain was actually a customer driven direction due to the progression of System On a Chip (SOC) design.  This shift resulted in a reducction of the “manufacturing supply chain” for a lot of systems to just a component level product, enclosures, memory and displays.  In the semiconductor supply chain, they are providing customized build solutions for equipment manufacturers to be able to “replica manufacture” their equipment, as designed in R&D, near the point of sale, application and support of the semiconductor wafer fab.  The supply chain includes both the wafer fab portion of the process as well as the electrical test, packaging and final test portions.  The emergence of the semiconductor target model has given rise it a market split of 50% in North America and 50% in Asia primarily in Penang and Shanghi.

This supply chain model, that has been implemented by Jabil, for expansion of the subcontract manufacturing community is the new model that companies are shifting to in order to address the reduced component count of mobile electronic systems and offset the high cost of transportation for people and materials.

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John introduced the subject of the panel by defining the scope of green power as it pertained to this panel.  The understanding was low power and power use efficiency has always been a criteria of design, just not one of top constraints.  Now, the shift has been made to address eco-friendly design which is a multi-domain, multi-sector, full design chain for both the component creation (IC) and the electronic system that uses the component.

The panelists discussed the background on the importance of “greening” the designs and the energy analysis focus on the IT portion.  Cadence indicated that it is a supply chain issue and the key was the identification and optimization of “energy productivity” which is a measure of useful power.

Cisco focused the discussions on the datacenter portion of the IT infrastructure as the energy target.  Nikhil identified that highest concentration of power use in the IT environment was the datacenters, and that most large installation now have an OPEX that exceed the CAPEX for these datacenters.  This places power as a high priority for a number of system applications.

IBM Venture Capital has been doing a lot of work in China and North America for the IT space.  The China market has 100% of it new design wins having a full identified energy efficiency target and power utilization form factor.  From an energy management perspective, the mobile marketplace is a “standby energy” market rather than an “active energy” market, and thus does not really enter into the full environment impact discussions as do the datacenters.  At this time, they are seeing over $1BUSD being spent for “green computing”, and growing.

Dr Rabaey made the connection that the base issues have been around for a long time and significant progress has been made, even with his own research, since the 1980’s.  The key to addressing and handling the energy efficiency issues is to quantify the use model through sensors to drive data collection and analysis.  This will provide the basis to develop deterministic models for energy use corrolated to activities of the equipment and then optimization techniques can be developed and applied.  This concept was referred to as a “societal information technology network”.

Carl started his discussion with the observation that when David Packard started the SVLG over 30 years ago, one of the key issues was energy use.  The eco-system for IT in both centralized and distributed implementations, is a system that is beyond on the scope of full modeling for engineering optimization at this time.  The need for this optimization and the driving factor on energy efficiencies of these datacenters is they currently consume 1.5% of the total energy used in the US and it is growing.  The solution to this problem and the reduction of energy use is going to have to be a collaborative task from members of the whole supply chain in the IT datacenter market.

The panel discussed aspects of the problem and summarized the panel with the observation that the solution was a multi-domain solution covering electrical / mechanical / thermal / and software related issues.  The consensus of the panelists was that the solution path the most immediate and supportable solutions would be a hardware based solution rather than a software solution.  This hardware would be deterministic in design and the use optimization would be provided by targeted application specific software.

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IDF kicked off by a well attended keynote by Craig Barrett. Rather than just talk about new process clock rates and how many cores can you hang on a single bus, he discussed the societal aspects of the technology and the deployment of technology with some livefeeds of distance medical diagnostics. In addition to the overview of the technical architecture of the new quad core chip, There were demonstrations of the new Nehalem included computer intensive CAD modeling, high throughput video, multiple data stream processing and high memory capacity systems (128GB+ RAM) configurations on a dual processor board. Although the processors were being shown, the staff in the demo booths, indicated the Core I7 ™ would not be available until late Q4′08 to early Q1′09 timeframe.

In addition to the high performance platforms, Intel introduced a number of chipsets/board level products for other markets. In the multimedia space, there were two system combos introduced (1) the DG45ID board which supports the Core(tm) 2 processors and Dolby Home Theater ™ processing; and (2) the DG43NB which uses the dual and quad core Core(tm) 2 chips.

They also introduced low power chipsets and re-introduced the Centrino 2 ™ platform. These were shown in new notebook products, netbooks (internet targeted thin client notebooks) and MID (mobile internet devices). A note of particular interest, of the 19 MIDs on display at the show, 17 were running Linux as thier only or primary OS, 2 were exclusively Windows on Win XP, and a total of 7 would also operate with WinXP or Vista.

Following the trend of several other companies, Intel introduced an Nand Flash based SSD. They have both product types SLC and MLC ranging in capacity from 32GB to 160GB drives. The drive family supports SATA and ONFI 1.0 as interfaces. In the 2.5″ form factor, they introduced and extreme SATA SSD with SLC Flash in 32 and 64Gb capacities. These server targed SLC drives (such as the X25e) feature 70us latency, Read data rates of 250MB/s, and Write data rates of 170MB/s. In the more mainstream products they introduced both 1.8″ and 2.5″ form fact with an 85us latency. The products are spec’d at a 5ye useful life in client PC application and are using 50nm Flash memory.

The drives were also presented in a smaller form factor as an OEM drive for MID, UMPCs, automotive and other space critical applications. These products utilize the same technology as the 1.8″ and 2.5″ products. The demonstrations at the product announcement were shown with a proprietary controller using the ONFI 1.0 interface and presented a 175X improvement in performance when compared to a traditional 2.5″ notebook computer drive. On the exhibit floor, the SSDs were being demonstrated with a streaming video application which did not exhibit the bit error rate problems of multiple streams of 720p data on a std HDD. The drives on the exhibit floor were all being demonstrated with SATA interfaces, so the performance was not on the same level as the product introduction demo.

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Synaptics has a number of new products and technology solutions that address far more than the PC pointer market. Most of these new products leverage the Synaptic’s proprietary IP for support and recognition of chiral motion. As a result, the new products support advanced gesturing, scrolling & sliders in a humidity and temperature variation stable solution.

Their new technologies support a dual mode which is a two dimensional (2D) touch pad supporting cursor motion and a second mode can fixed location for “tap” buttons on the same touch pad surface. To simplify the user interface for the two modes, the button mode can be back lit to display icons for the button locations, and then toggle the icons off to restore the pad to standard mode.

These advancements have also lead to the development of 1 dimensional (1D) and 2D clear touch pads that can also support external single touch traditional buttons. These clear products are being used in cell phones, and other mobile devices. The simpler 1D products support software driven icons that can be displayed under the button which change with the function mode. This is a preferred solution over printing multiple labels (e.g. a number, an arrow, an option string, a letter) all on a single button.

The clear touch pads are also being integrated into monitors and PC products to produce an improved level of industrial design. The clear touch pads are part of a “hidden” button design that have the back lighting on the sensors “black out” when not needed, leaving the end product with a very clean look. Additionally, these new sensors work on a proximity basis in addition to traditional touch. This allows the buttons to be illuminated and displayed only when the user gets near the buttons but before you contact them. This similar technology can be used in remote controls and other “open display” products.

The touch pads are also energy efficient. A large 2D touchpad which might be used for a full screen MID would utilize only 600uA in active mode, and then power down to about 10% or 60uA for standby mode.

At this time, the Synaptics products are being sold into the consumer, PC, and mobile telecommunications market and activiy is continuing to review possible expansion to the medical and industrial application space.
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