Comments for Pallab's Place

Comment on DAC and IPV6- a big June ahead by admin

admin — Thu, 26 May 2011 17:25:18 +0000

The link is now fixed for IE and Firefox – I posted it with Chrome originally.

Comment on DAC and IPV6- a big June ahead by Jonathan

Jonathan — Thu, 26 May 2011 17:18:56 +0000

the link to world IPV6 day is broken. (at least in firefox..)

Comment on Devices and Litho for sub 17nm process by admin

admin — Fri, 19 Nov 2010 19:49:21 +0000

IF EUV is not ready – either by stability of technology or throughput, then it appears quad and triple patterning will dominate the sub 15nm nodes. Self assembly is still in the background for the sub 10nm technologies, but there is still work on the getting usable patterns with that technology. The consensus was that with or without EUV, 15nm is happening on schedule, it is up to the EUV folks to make it to the event on time.

Comment on Devices and Litho for sub 17nm process by Richard Goering

Richard Goering — Fri, 19 Nov 2010 18:30:56 +0000

This is an interesting look at what lies below 22nm. It seems to me there are two scenarios — one with EUV (which seems to be the expected one), and one without EUV. Has there been much thinking about what happens if EUV is not available by 15nm? Will it still be a viable, affordable node, or will it be out of reach for all but a small handful of companies with extremely large pocketbooks?

Comment on NXP IPO – a snapshot of industry health by admin

admin — Mon, 09 Aug 2010 16:31:05 +0000

Nope, not the same one. He is a process guy and still involved with the industry and IEEE down in TX. I am from the mixed signal and design side.

Comment on NXP IPO – a snapshot of industry health by Subhas Basu

Subhas Basu — Mon, 09 Aug 2010 15:50:18 +0000

Good to hear!

Just curious to know if you are Dr Pallab Chatterjee from Texas Instruments?

Comment on 3D Packaging brings New Design Challenges by Ed Malloy

Ed Malloy — Fri, 11 Jun 2010 19:26:52 +0000

It was an interesting Symposium and the latest IMS3TW conference was another opportunity to delve into these crtical topics.

Ensuring the right test infrastructure is inserted during logic design combined with methods for ensuring high-quality silicon with fewest test escapes will be an important trade-off in order to capture the potential value of 3D Stacking or 3D SIP.

Thx
Ed Malloy
Cadence Design Systems

Comment on Playstation Move – Motion Controller at GDC by Kenny

Kenny — Sat, 13 Mar 2010 13:23:21 +0000

Who makes the 3 axis Gyroscope and the 3 Axis Accelerometer used in the Move?

Comment on Network ICs – packaging is a key design element by Hillol Sarkar

Hillol Sarkar — Wed, 10 Feb 2010 18:03:49 +0000

Package is the second most expensive part next to Silicon.
It requires accurate Transmission Line Analysis and optimization.
AgO has developed Advanced Algorithm to optimize Analog and RF circuits.
It works with Spice Simulators. AnXplorer Design Data base after optimization can
enhance the alternative desired performance of Package IC integration path. Package simulation
is a complex process and Integrated tools are not available. Optimization can solve the manual
trial and error method. We have given an overview of the technology. http://bit.ly/d-pre

http://www.cst.com/Content/Applications/Article/IC+Package+Simulation

Above link has some useful discussion about transmission line simulation.

Hillol Sarkar

Comment on IEDM 2009 – NEC improves copper contacts for RF by Hillol Sarkar

Hillol Sarkar — Fri, 01 Jan 2010 05:10:36 +0000

Our optimization algorithm can enhance the design process targeted for Lte and various High Frequency Radio Technology for Broad Band Wireless.

hillol.sarkar@gmail.com
ago-inc.com