Archive for the 'Uncategorized' Category

Sep 24 2011

Energy Efficient Electronic Systems at UC Berkeley

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On Nov 3 & 4, 2011, the Center for E3S of  the EECS department is holding their second annual conference at the UC Berkeley campus.  This year’s event spans 2 days and has 19 confirmed speakers following a keynote to be presented by Dan Hutcheson of VLSI Research Inc .  This years symposium will cover a range of topics including:

Low voltage tunneling FETs;
Low voltage nanomechanical logic;
Energy efficient spintronic logic;
Energy efficient memory and storage devices;
Energy efficient chip scale interconnects; and
Low voltage CMOS circuits and architectures.

The center’s chair Dr. Eli  Yablonovitch will be speaking and showing off research activities in the group.  The center is focusing on the challenges of lowering the operating voltage of electronics and electronic systems and addressing the growing power that is being consumed by the aggregated IT infrastruture and connectivity that is pervasive in today’s society.  The E3S Center is responding to the challenge under the following charter:

“The Center for Energy Efficient Electronics Science (E3S) has been established to:

  • Open a new energy efficiency frontier in information technology by developing transformative science and technology that reduce energy consumption in electronic systems by orders of magnitude.
  • Inspire and train a diverse generation of scientists, engineers, and technicians that applies this new science and technology to benefit society.”

based on the quality and diversity of speakers, this events is shaping up to be the premier low power event on the west coast this year.  Information on the conference and registration is available at:

http://www.e3s-center.org/events/11/sym2011-home.htm/

 

Discounted early registration is available on the site through October 7.

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Sep 22 2011

TrueMask DS: Mask-Wafer Double Simulation Platform

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At the 2011 SPIE masking conference, known as BACUS, we had a chance to meet with and talk to Aki Fujimura of D2S, Inc about his company’s new product offering. The new platform is an interactive masking workstation that allows for simultaneous optimization of lithographic patterning for BOTH mask and the resulting wafer image.

The integrated software / workstation platform was created to address the discontinuity that has arrived at the sub-80nm (on mask feature size) / sub-20nm (on wafer feature size) nodes.The system works by having mask designers target highly critical areas and/or highly repetitive patterns up to 300umX300um (on mask). TrueMask DS allows the user to interactively trade-off the mask shot count and mask manufacturing margin with wafer manufacturing margin down to a resolution of 0.1nm on mask. The system also features Litho aerial simulation which helps feed the reduced interpretation time from running the 5umx5um (on wafer) object analysis. The graphic shows screen images that result from the various types of simulation.

Modeling results from TrueMask Mask-Wafer Double Simulation

The system helps bend the curve on mask costs. As current multi-million dollar mask cost explode due to multiple patterning and the need for complex shapes, this model based approach is targeting up to 25% cost savings for processing the shape set that is anticipated for the 15nm and below nodes. There is a corresponding shortening of the schedule along with the cost savings for the materials. As the system support eBeam sources, the system can simulate rectilinear, overlapping and in the future, variable shaped beam sources.

At 20nm feature size, the amount of OPC (Optical Pattern Correction) and SRF (Sub-Resolution Features) that is required to correctly represent the layout feature is very high. The features require many complex mask shapes, which may not be repeated based on context over large reach areas. The tool set reads GDSII and OASIS data and can interface with SEM for inspection of both mask and wafer patterns.

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Aug 28 2011

Unity Semiconductor Update – August 2011

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At the Flash Memory Summit, we had a chance to meet with David Eggleston who is the CEO of Unity Semi.  The RRAM company has recently re-targeted its business model.  The new model is based on a traditional IP licensing structure which includes process, design and scalability licenses.  The IP is based in part on their 120 patents for the CMOX cell technology that have been granted, and the over 100 that are in process.
The current portfolio of IP includes cells, product and macro designs, architectures, and application support (interface design, SDKs, etc).  They have announced one licensee which is Micron Technology which announced a 2 year JDP starting in 2010.
Currently the company is receiving 1/3 of its revenue from product sales and design/process services with their fab lite model.  They are targeting fabs, IDM and ODMs as licensing partners.
The company was formed in 2002, and created the first CMOX cells in 2004.  The cells are available in single bit (SLC), dual bit (MLC) and triple bit (TLC) data architectures. Backers Seagate and Micron are driving the technology for cloud based applications of active memory with a new optimization point for capacity, performance, ease of use and low cost.
The page based memory are moving towards a cents/GB cost with 1TB Capacity, and performance in the 500Mb/s R & 200Mb/s W range.
PC

At the Flash Memory Summit, we had a chance to meet with David Eggleston who is the CEO of Unity Semi.  The RRAM company has recently re-targeted its business model.  The new model is based on a traditional IP licensing structure which includes process, design and scalability licenses.  The IP is based in part on their 120 patents for the CMOX cell technology that have been granted, and the over 100 that are in process.

The current portfolio of IP includes cells, product and macro designs, architectures, and application support (interface design, SDKs, etc).  They have announced one licensee which is Micron Technology which announced a 2 year JDP starting in 2010.

Currently the company is receiving 1/3 of its revenue from product sales and design/process services with their fab lite model.  They are targeting fabs, IDM and ODMs as licensing partners.

The company was formed in 2002, and created the first CMOX cells in 2004.  The cells are available in single bit (SLC), dual bit (MLC) and triple bit (TLC) data architectures. Backers Seagate and Micron are driving the technology for cloud based applications of active memory with a new optimization point for capacity, performance, ease of use and low cost.

The page based memory are moving towards a cents/GB cost with 1TB Capacity, and performance in the 500Mb/s R & 200Mb/s W range.

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Aug 28 2011

New Memory – MRAM at Flash Mem Summit

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At the Flash Memory Summit in August, there was a non-Flash session dealing with new memory technologies.  It covered both RRAM and MRAM also known as Resistive RAM and Magnetic RAM technologies.
The Magnetic RAM (MRAM) arena also presented an technology update.  The updates were from Avalanche Tech, Corcus, Everspin, MagSil and new startup Spin Transfer Technology.  Avalanche Tech lead things off with an update of their 3rd Generation MRAM product which is a spin programable memory.  The structure is best fit att addressing the SLC NOR and embedded SLC marketplace since it has a fast switching time (under 1ns) and is 3D stack-able to approach the high densities.  The product can also be configured to DRAM type applications, which make it a good universal memory product for both the controller interface and product store of Enterprise class SSDs.
Crocus discussed some of the details on their new JDP with a Russian Nanoelectronics Corp which will be investing $300M to bring up a 12″ fab for the technology.  The technology is base on an MLU concept (Magnetic Logic Unit) block that has it’s memory element from a TAS (Thermaly Assisted Switching) technology.  The MLU implements a “native XOR” function in the cell design.  The new strucutre is a self differential cell that supports high temperature operation and assembly (200C operation).  The Crocus designs are applicable for NAND replacement, MLC applications, and both CAM/TCAM uses.
MagSil, a seven year old fabless startup gave an overview of thier technology which has been designed in 180nm and is extensible to 18nm without physics changes.  They have been concentrating on solving the field issues related to the switching of magnetic films and have now developed solutions that are compatible with both Copper (Cu) and Aluminum (Al) interconnect solutions.  They are expecting sample parts to be available in the 2013 time frame.
A new entry to the MRAM arena is Spin Transfer Technology (STT) which described an Orthoganal Spin Transfer (OST) technology.  This type of MRAM has a structured, deterministic switching torque.  This characteristic can be used to drive for instant on-instant off memory applications for the mobile marketplace.  The technology, tested to the block level so far, has a 99% probability of <1ns switching between states.
The last update was from Everspin, which is the only company that is commercially shipping MRAM products to applications.  Their customers include Airbus and BMW, and theiy have shipped 3M pcs to date.  Thier fab light model includes thier BEOL fab for the MRAM using base layers built by commercial CMOS foundry.  They currently have over 70 product SKUs and their main use is in SPI SRAM replacement.  The durability of the product is proven by the application from Airbus which is the memory for the blackbox.

At the Flash Memory Summit in August, there was a non-Flash session dealing with new memory technologies.  It covered both RRAM and MRAM also known as Resistive RAM and Magnetic RAM technologies.

The Magnetic RAM (MRAM) arena also presented an technology update.  The updates were from Avalanche Tech, Corcus, Everspin, MagSil and new startup Spin Transfer Technology.  Avalanche Tech lead things off with an update of their 3rd Generation MRAM product which is a spin programable memory.  The structure is best fit att addressing the SLC NOR and embedded SLC marketplace since it has a fast switching time (under 1ns) and is 3D stack-able to approach the high densities.  The product can also be configured to DRAM type applications, which make it a good universal memory product for both the controller interface and product store of Enterprise class SSDs.

Crocus discussed some of the details on their new JDP with a Russian Nanoelectronics Corp which will be investing $300M to bring up a 12″ fab for the technology.  The technology is base on an MLU concept (Magnetic Logic Unit) block that has it’s memory element from a TAS (Thermaly Assisted Switching) technology.  The MLU implements a “native XOR” function in the cell design.  The new strucutre is a self differential cell that supports high temperature operation and assembly (200C operation).  The Crocus designs are applicable for NAND replacement, MLC applications, and both CAM/TCAM uses.

MagSil, a seven year old fabless startup gave an overview of thier technology which has been designed in 180nm and is extensible to 18nm without physics changes.  They have been concentrating on solving the field issues related to the switching of magnetic films and have now developed solutions that are compatible with both Copper (Cu) and Aluminum (Al) interconnect solutions.  They are expecting sample parts to be available in the 2013 time frame.

A new entry to the MRAM arena is Spin Transfer Technology (STT) which described an Orthoganal Spin Transfer (OST) technology.  This type of MRAM has a structured, deterministic switching torque.  This characteristic can be used to drive for instant on-instant off memory applications for the mobile marketplace.  The technology, tested to the block level so far, has a 99% probability of <1ns switching between states.

The last update was from Everspin, which is the only company that is commercially shipping MRAM products to applications.  Their customers include Airbus and BMW, and theiy have shipped 3M pcs to date.  Thier fab light model includes thier BEOL fab for the MRAM using base layers built by commercial CMOS foundry.  They currently have over 70 product SKUs and their main use is in SPI SRAM replacement.  The durability of the product is proven by the application from Airbus which is the memory for the blackbox.

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Aug 28 2011

New Memories- RRAM at Flash Mem Summit

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At the Flash Memory Summit in August, there was a non-Flash session dealing with new memory technologies.  It covered RRAM and MRAM also known as Resistive RAM and Magnetic RAM technologies.
The summit is well known for showcasing new technologies, in the past few years, the emphasis has been on Phase Change Memories as the leading alternate technology, and that technology has now moved into commercial production.
The Resistive RAM session (RRAM) is technologies utilizing the resistive characteristics of the Oxygen Molecule in a crystalline lattice.   The companies presenting updates were Unity, Sony, HP Labs and Adesto.  The sector actually has two base technologies – ReRAM which is the resistive oxygen, and CBRAM which is based on resistance of the conductive filaments in the RAM cell.
Unity and HP Labs discussed their movement towards the high capacity (1TB) storage of a multi-layer cross point memory.  The HP Lab product is utilizing the MEMRISTOR technology that is built using a TiO2 cell with Pt Caps.  The Unity solution is also using an Oxygen movement mechanism in their CMOX technology.   Both are targeted for high capacity active storage applications.
Sony’s Emerging Memory group discussed ther new NVM for RRAM which is based on an an electrolytic cell made with CuTe and a select transistor.  This cell was recently built as a 4MB test macro, and the results were presented in detail at ISSCC 2011 in Feb of this year.  The resulting block was able to perform data througput at 2.3Gb/s with 100ns of latency.
Adesto discussed their Conductive Bridging RAM.  This is also a RAM type device application and has a new corner on the feature optimization.  The product is targeted at tradeoff optimization for write performance, write endurance, data retention and low power operation.  The technology should be sampling in the 2nd half of 2011, and there are several customers who are awaiting the samples for their systems.
These technologies are looking to be in volume production in the 5-10 year time frame.
PC

At the Flash Memory Summit in August, there was a non-Flash session dealing with new memory technologies.  It covered RRAM and MRAM also known as Resistive RAM and Magnetic RAM technologies.

The summit is well known for showcasing new technologies, in the past few years, the emphasis has been on Phase Change Memories as the leading alternate technology, and that technology has now moved into commercial production.

The Resistive RAM session (RRAM) is technologies utilizing the resistive characteristics of the Oxygen Molecule in a crystalline lattice.   The companies presenting updates were Unity, Sony, HP Labs and Adesto.  The sector actually has two base technologies – ReRAM which is the resistive oxygen, and CBRAM which is based on resistance of the conductive filaments in the RAM cell.

Unity and HP Labs discussed their movement towards the high capacity (1TB) storage of a multi-layer cross point memory.  The HP Lab product is utilizing the MEMRISTOR technology that is built using a TiO2 cell with Pt Caps.  The Unity solution is also using an Oxygen movement mechanism in their CMOX technology.   Both are targeted for high capacity active storage applications.

Sony’s Emerging Memory group discussed ther new NVM for RRAM which is based on an an electrolytic cell made with CuTe and a select transistor.  This cell was recently built as a 4MB test macro, and the results were presented in detail at ISSCC 2011 in Feb of this year.  The resulting block was able to perform data througput at 2.3Gb/s with 100ns of latency.

Adesto discussed their Conductive Bridging RAM.  This is also a RAM type device application and has a new corner on the feature optimization.  The product is targeted at tradeoff optimization for write performance, write endurance, data retention and low power operation.  The technology should be sampling in the 2nd half of 2011, and there are several customers who are awaiting the samples for their systems.

These technologies are looking to be in volume production in the 5-10 year time frame.

PC

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Jul 30 2011

Challenge not only with Litho

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As semiconductor processes get smaller, the focus has been on patterning methods for realizing these devices on the wafer.  This is not the only challenge that is facing the cutting edge of the semi industry.  An equal issue is the metrology to determine if these patterns are created properly.
Wafer metrology deals with the measurement of planarity issues, etched structure size and uniformity along with both vertical and horizontal aspects of deposited and grown layers.  A number of these steps are optical in nature and the inspection of the wafers should not exceed the time taken to create the patterns.  As a result, the same issues, variability and uncertainty that plagues litho, also plagues metrology.
At the Semicon event this year, a number of companies were showing new solutions based on particle beam technology and other techniques.  The other techniques include Photomask Metrology, SEM, Optical Linescale, and Atomic Force Microscopy and Nanoparticle Manipulation Metrology.  To help the industrial sector NIST (http://www.nist.gov/pml/div681/grp14/) Has also been working on this area creating references against which methods can both be calibrated and measured.
One of the biggest issues with current metrology is identifying non-destructive and non-invasive techniques for measuring in-silicon properties such as strained channels, STI, and other “engineered materials” steps that are mainstream in today’s processes.  These metrology methods are key to the continuing trend toward outsourced manufacturing, as it is the methrics upon which the wafers are sold, rather than on a functioning die basis.
Companies with major announcement in this area at the event included Nanometrics and KLA.
PC

As semiconductor processes get smaller, the focus has been on patterning methods for realizing these devices on the wafer.  This is not the only challenge that is facing the cutting edge of the semi industry.  An equal issue is the metrology to determine if these patterns are created properly.

Wafer metrology deals with the measurement of planarity issues, etched structure size and uniformity along with both vertical and horizontal aspects of deposited and grown layers.  A number of these steps are optical in nature and the inspection of the wafers should not exceed the time taken to create the patterns.  As a result, the same issues, variability and uncertainty that plagues litho, also plagues metrology.

At the Semicon event this year, a number of companies were showing new solutions based on particle beam technology and other techniques.  The other techniques include Photomask Metrology, SEM, Optical Linescale, and Atomic Force Microscopy and Nanoparticle Manipulation Metrology.  To help the industrial sector NIST, has also been working on this area creating references against which methods can both be calibrated and measured.

One of the biggest issues with current metrology is identifying non-destructive and non-invasive techniques for measuring in-silicon properties such as strained channels, STI, and other “engineered materials” steps that are mainstream in today’s processes.  These metrology methods are key to the continuing trend toward outsourced manufacturing, as it is the methrics upon which the wafers are sold, rather than on a functioning die basis.

Companies with major announcement in this area at the event included Nanometrics and KLA.

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Jul 29 2011

Semicon Expanding Markets

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Semi (www.semi.org), the group behind Semicon, has had a long history of supporting the semiconductor ecosystem – materials, equipment, test and manufacturing.  The majority of the past 4 decades the organization has focused on mainstream semiconductor circuits in Silicon and GaAs.  The large diversity of fabs that were owned and variation in process methods, made for a very large ecosystem.
Over the years the foundry model has moved into play, and there are only a few very large IDMs with new fabs, so the mainstream semiconductor manufacturing core is dramatically reduced in number.  However, Semi and the Semicon show have adapted.
This years show, not only embraced, but featured the following high growth areas, each of which requires specialty materials and equipment to product semiconductor products.  The biggest area of growth is Photovoltaics (PV) which, with the co-location of the Intersolar conference features an equal number of attendees and more exhibitors than Semicon.  Other fast growth areas include LEDs and Lighting, Flat Panel Displays (FPD), Micro-electromechanical systems (MEMS), Printed / organic / flexible electroncis and related areas of in-manufacturing metrology & test along with packaging and finished product test.
LEDs (and generalized silicon photonics), FPD, and MEMS have long been staples of the semiconductor industry, but in the past, they were relegated to private shows in thier own niche ecosystem.  The direction of stacked die and 3D Ics is driving the mixed technology end products, which now need to keep these altenate technologies in the main ecosystem.  The need to keep them in the main flow is it insure the quality benefits, processing benefits and logistics benefits that have been made for CMOS are available in these technologies.
PC

Semi (www.semi.org), the group behind Semicon, has had a long history of supporting the semiconductor ecosystem – materials, equipment, test and manufacturing.  The majority of the past 4 decades the organization has focused on mainstream semiconductor circuits in Silicon and GaAs.  The large diversity of fabs that were owned and variation in process methods, made for a very large ecosystem.

Over the years the foundry model has moved into play, and there are only a few very large IDMs with new fabs, so the mainstream semiconductor manufacturing core is dramatically reduced in number.  However, Semi and the Semicon show have adapted.

This years show, not only embraced, but featured the following high growth areas, each of which requires specialty materials and equipment to product semiconductor products.  The biggest area of growth is Photovoltaics (PV) which, with the co-location of the Intersolar conference features an equal number of attendees and more exhibitors than Semicon.  Other fast growth areas include LEDs and Lighting, Flat Panel Displays (FPD), Micro-electromechanical systems (MEMS), Printed / organic / flexible electronics and related areas of in-manufacturing metrology & test along with packaging and finished product test.

LEDs (and generalized silicon photonics), FPD, and MEMS have long been staples of the semiconductor industry, but in the past, they were relegated to private shows in thier own niche ecosystem.  The direction of stacked die and 3D Ics is driving the mixed technology end products, which now need to keep these altenate technologies in the main ecosystem.  The need to keep them in the main flow is it insure the quality benefits, processing benefits and logistics benefits that have been made for CMOS are available in these technologies.

PC

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Jun 30 2011

ARM Mali GPU Unifying graphics across platforms

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ARM recently had an update announcement on their Mali GPU.  The RTL level core has now been licensed by 46 parties, of which 6 have released products and are royalty paying partners.  This new core is the engine in the Samsung Galaxy S2 phone.
The goal of the Mali program is to be able to deliver high performance graphics capabilities, at higher resolutions but with the same power budget.  The shifting application space is requiring the same user experience for phones, tablets, netbooks/laptops, standard display monitors and large screen. This range includes small sub 3″ displays at VGA through 60hz 4K2K displays. The performance of the displays has to compensate for the changes in memory bandwidth and the driver power for these external memories.  The GPU block is designed to be optimized for the ARM CPUs and minimize external memory calls which consume more power.  (Fig 1)
The multi-core design is set for large data and scaling with a DX7 style API and providing performance at levels that are DirectX11 compatible for desktops (5Gpixel/sec or 250GFLOPS)  and Open GL ES2.0 for mobile (1.5Gpixel/sec or 25GFLOPS).  In addition to these increasing data rates, to maintain image quality, there is more processing per pixel.  The same processing core must also handle use UI’s such as touch, gesture, multi-touch, 3D and other technologies that are both engaging and also provide a simplifying user experience;
The Mali-T604 uses the “Midgard” GPU architecture. (Figure 2).  The core is scalable up to 4 cores, and supports the full profile of OpenCL, OpenGL ES and Open VG as well as Microsoft DirectX up to V11.  The key for the GPU line (which is Android OS optimized) is to be brought to market after the 2006 acquisition of Falanx, as the graphics portion of the devices becomes more dominant.  The products are entering late into the market, and hoping to catch up on the coattails of their processor core dominance.  The core is directly in the marketplace competing against entrenched products form Nvidia, Imagination Technologies, Intel, Qualcomm, Marvell and others.
PC

ARM recently had an update announcement on their Mali GPU.  The RTL level core has now been licensed by 46 parties, of which 6 have released products and are royalty paying partners.  This new core is the engine in the Samsung Galaxy S2 phone.

The goal of the Mali program is to be able to deliver high performance graphics capabilities, at higher resolutions but with the same power budget.  The shifting application space is requiring the same user experience for phones, tablets, netbooks/laptops, standard display monitors and large screen. This range includes small sub 3″ displays at VGA through 60hz 4K2K displays. The performance of the displays has to compensate for the changes in memory bandwidth and the driver power for these external memories.  The GPU block is designed to be optimized for the ARM CPUs and minimize external memory calls which consume more power.  (Fig 1)

ARM Mali GPU and CPU Architecture

ARM Mali GPU and CPU Architecture

The multi-core design is set for large data and scaling with a DX7 style API and providing performance at levels that are DirectX11 compatible for desktops (5Gpixel/sec or 250GFLOPS)  and Open GL ES2.0 for mobile (1.5Gpixel/sec or 25GFLOPS).  In addition to these increasing data rates, to maintain image quality, there is more processing per pixel.  The same processing core must also handle use UI’s such as touch, gesture, multi-touch, 3D and other technologies that are both engaging and also provide a simplifying user experience.

ARM Mali T604 Overview

ARM Mali T604 Overview

The Mali-T604 uses the “Midgard” GPU architecture. (Figure 2).  The core is scalable up to 4 cores, and supports the full profile of OpenCL, OpenGL ES and Open VG as well as Microsoft DirectX up to V11.  The key for the GPU line (which is Android OS optimized) is to be brought to market after the 2006 acquisition of Falanx, as the graphics portion of the devices becomes more dominant.  The products are entering late into the market, and hoping to catch up on the coattails of their processor core dominance.  The core is directly in the marketplace competing against entrenched products form Nvidia, Imagination Technologies, Intel, Qualcomm, Marvell and others.

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Jun 30 2011

Nividia & Microsoft C+ + AMP update

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With the rise of multi-core systems and distributed computing, the performance optimization is also spreading to using both CPU and GPU as the compute engines in software.  The fundamental architectural distinction between the two are CPUs are sequential cores and GPUs are primarily parallel pipeline style cores optimized for computation.  Currently, such code is written in Fortran, Java, Python and with direct addressed functions from the GPU provider = C+ +.  Microsoft is dedicated to supporting Heterogeneous Parallel Computing across multi-core, distributed core, cloud cores and mixed CPU/GPGPU systems with a new standard extension to C+ + called C+ + AMP.  The C+ + AMP (accelerated massive parallelism) compiler should return the C+ + programming language to being, as claimed by Microsoft, the best performance/watt of any other development environment.
The AMP extension was chosen to be added to C+ + rather than C as it is a more mainstream language and the selection was to future proof the extension with the popularity of the language.  The extension is based on Lambda functions/objects and are documented as part of the C+ +Ox extensions for compute awareness.  The C+ + AMP extension is characterized by the addition of the Array_view and Restrict keywords.   The syntax for restrict(class) is to identify a parallelized  or serialized CPU.    For example restrict(direct3d) indicates execution by any DirectX11 GPU device.
To help simplify the tasks of memory mapping between multiple architectures, clearing and grouping the low level parallelization of the code, the optimally using the available cores, the C+ +AMP extensions have been included in Microsoft Visual Studio.    This allows for the full visual development and debug environment, including the suppress errors/messages, that has been the hallmark of the C+ + development.
Nvidia also showed new extensions to the CUDA primative language and the new release of Thrust v4.0.  Thrust is a CUDA library of parallel algorithms with an interface resembling the C+ + Standard Template Library (STL). Thrust provides a flexible high-level interface for GPU programming that enhances developer productivity   (http://code.google.com/p/thrust/) Thie new Thrust library allows for those using standard C+ + compilers (those not enabled with AMP extensions).  This open source high level library eliminates the details of determining the parallel granularity of blocks and threads as well as handling the getting data between the CPU memory and GPU memory and not either stranding data or operating on out of sync data.
PC

With the rise of multi-core systems and distributed computing, the performance optimization is also spreading to using both CPU and GPU as the compute engines in software.  The fundamental architectural distinction between the two are CPUs are sequential cores and GPUs are primarily parallel pipeline style cores optimized for computation.  Currently, such code is written in Fortran, Java, Python and with direct addressed functions from the GPU provider = C+ +.  Microsoft is dedicated to supporting Heterogeneous Parallel Computing across multi-core, distributed core, cloud cores and mixed CPU/GPGPU systems with a new standard extension to C+ + called C+ + AMP.  The C+ + AMP (accelerated massive parallelism) compiler should return the C+ + programming language to being, as claimed by Microsoft, the best performance/watt of any other development environment.

The AMP extension was chosen to be added to C+ + rather than C as it is a more mainstream language and the selection was to future proof the extension with the popularity of the language.  The extension is based on Lambda functions/objects and are documented as part of the C+ +Ox extensions for compute awareness.  The C+ + AMP extension is characterized by the addition of the Array_view and Restrict keywords.   The syntax for restrict(class) is to identify a parallelized  or serialized CPU.    For example restrict(direct3d) indicates execution by any DirectX11 GPU device.

To help simplify the tasks of memory mapping between multiple architectures, clearing and grouping the low level parallelization of the code, the optimally using the available cores, the C+ +AMP extensions have been included in Microsoft Visual Studio.    This allows for the full visual development and debug environment, including the suppress errors/messages, that has been the hallmark of the C+ + development.

Nvidia also showed new extensions to the CUDA primative language and the new release of Thrust v4.0.  Thrust is a CUDA library of parallel algorithms with an interface resembling the C+ + Standard Template Library (STL). Thrust provides a flexible high-level interface for GPU programming that enhances developer productivity   (http://code.google.com/p/thrust/) Thie new Thrust library allows for those using standard C+ + compilers (those not enabled with AMP extensions).  This open source high level library eliminates the details of determining the parallel granularity of blocks and threads as well as handling the getting data between the CPU memory and GPU memory and not either stranding data or operating on out of sync data.

PC

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May 25 2011

DAC and IPV6- a big June ahead

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The EDA and design community usually looks forward to the first day of DAC (Design Automation Conference) with excitement.  Not only is it Free Exhibits Monday, but the directions for tools and issues that are being address by the EDA community with products and partners are usually announced.  These announcements focus on the capabilities of the advanced processes to actually have design support information available to designers other than those from the 2-3 joint development companies.   These announcements and the tools vendors also address the reality of which process nodes the designs are being built.  This is the usual buzz in the industry, and this year takes place on Monday June 6th.
The buzz may not be long lived as there is another big happening on Wed 6/8, which will actually have more impact on designers that promised release of tools that aren’t quite ready and IP that is not quite frozen.  The official internet launch and support of a test run for IPV6 which happens on Wednesday 6/8. World IPV6 Day (http://isoc.org/wp/worldipv6day/) is a 24hour test run of websites, network hardware, operating systems, and ISPs to see if the new addressing scheme works.  The necessity of IPV6 is becauser we are running out of IP addresses for devices and web destinations under the IPV4 system.
This change ripples through all levels of the design hierarchy, and the larger address size will end up impacting throughput, performance, memory cycling, effective response time and connectivity handshake for any wired or wireless device that needs to have network connectivity.  The change effects products in production and in early phase design, because the IPV4 compatibility is not permanent, and has to be upgraded to the new IPV6 stadards for long terms use.   Details on the switch and the new specifications can be found at The Internet Engineering Task Force web site http://www.ietf.org/   The spec itself can be found at http://www.ietf.org/rfc/rfc2460.txt .  The fundamental changes is IPv6 increases the IP address size from 32 bits to 128 bits.  There are a number of other details, but that shift is the major one which will effect embedded and custom designs.
These two events, are going to make for an interesting June.
PC

The EDA and design community usually looks forward to the first day of DAC (Design Automation Conference) with excitement.  Not only is it Free Exhibits Monday, but the directions for tools and issues that are being address by the EDA community with products and partners are usually announced.  These announcements focus on the capabilities of the advanced processes to actually have design support information available to designers other than those from the 2-3 joint development companies.   These announcements and the tools vendors also address the reality of which process nodes the designs are being built.  This is the usual buzz in the industry, and this year takes place on Monday June 6th.

The buzz may not be long lived as there is another big happening on Wed 6/8, which will actually have more impact on designers that promised release of tools that aren’t quite ready and IP that is not quite frozen.  The official internet launch and support of a test run for IPV6 which happens on Wednesday 6/8.   World IPV6 Day is a 24hour test run of websites, network hardware, operating systems, and ISPs to see if the new addressing scheme works.  The necessity of IPV6 is becauser we are running out of IP addresses for devices and web destinations under the IPV4 system.

This change ripples through all levels of the design hierarchy, and the larger address size will end up impacting throughput, performance, memory cycling, effective response time and connectivity handshake for any wired or wireless device that needs to have network connectivity.  The change effects products in production and in early phase design, because the IPV4 compatibility is not permanent, and has to be upgraded to the new IPV6 stadards for long terms use.   Details on the switch and the new specifications can be found at The Internet Engineering Task Force web site,  the spec itself can be found at http://www.ietf.org/rfc/rfc2460.txt .  The fundamental changes is IPv6 increases the IP address size from 32 bits to 128 bits.  There are a number of other details, but that shift is the major one which will effect embedded and custom designs.

These two events, are going to make for an interesting June.

PC

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