Pallab’s Place

This year DAC is being touted as the “Year of Analog”.  Yet again, another under-developed sector, that has customers without a budget, and that require a very large diversity of solutions around very few core engines is supposed to be EDA’s salvation.

I agree on many aspects that the Analog and Mixed Signal markets have been under-served by EDA, and as a result there are now many tool vendors suppling products into the space, however the real solution providers in this space took a long time to get to the market, stabilize their products and work with the customers to develop usable solutions.  This is not the quick entry marketplace due to the voluminous legacy data (over 30 years worth) that exists and needs to “participate” in the new tool environment.

The better title would be “Year of Device Level Design”.  Then all the digital IP libraries being rightfully redesigned and ported to new sub-wavelength processes using re-architectured and re-engineered device level tools would be the market.  This market has budgets, customers and is more systematic from a tool requirement and use model perspective.

In any event, it is “analog” so the belief is that the real designers working at any level below verilog will now have new tools.  In my short review of products appearing at DAC, I have based by comments either on (A) prior design knowledge of either directly working with the products, or working with customers working directly with the products, or (B) new assessment of the product based on the capabilities of the DAC demo and the ability for the floor staff to intelligently answer simple questions about their company and products.

[NOTE: Due to an abreviated DAC Schedule, I did not get a chance to visit AWR or Magma, their product reviews will appear next week as another editor James Benouis covered their products]

Vendors who knew what Polygon Layout, Schematic Capture, Netlist, and Device Simulators were used for, had customers, and had product demo that indicated such:
Simucad, Berkeley Design Automation, Solido, Pulsic, SpringSoft, Mentor, Synopsys (simulator products only)

On the right track, but still early stage :
SynCira, Ciranova (PhyCell Studio only), Nassentric, Synopsys (custom layout)

Without a clue :
The REST of the DAC exhibitor with layout editors and new simulators and most of the new and old products from these suppliers.

This assessment was based on their global inability to answer the following questions for the product or have a demo that any remotely related to useful steps of the analog design process.
Q1    What database format can your read in and out for going to mask or legacy design capture?
Q2    What simulation / verification / DFM tool do you interface with and with what data format?
Q3    Can you hardcopy (make a printout) of any of the stuff on the screen?
Q4    Do you have any fab or EDA relationships to get the tech file info?
Q5    Has anyone at your company actually designed an analog block and released it to a fab for manufacture and test - and been responsible for those stages - at your company?
Sadly, the majority of “new Analog companies” to save EDA were averaging having an answer for only 1 out of 5 and that was Q3 - with a general answer of NO.

Not a happy day in EDA and Analog town - just another one, with the Cadence Analog tools still holding the majority of the new license and maintenance market.

PC

The keynotes RSA Conference held in San Francisco followed the theme that data Security is no longer an option, it is required.  This was reiterated several times by RSA president Art Coviello who also noted the dialog box pop-up of “Are you sure?” before you submit information is the tech worlds equivalent of the old movie line “Do you feel lucky?”.  A later keynote by Dept of Homeland Security Secretary Michael Chertoff identified today’s threat of cyberspace is on a par with 9/11.  Replays of the conference keynotes are available after registration at the following site:

In a move that emphasizes the direction of security, Hitachi recently purchased the long standing private company M-Tech, now called Hitachi ID.  The M-Tech acquisition fills that gap in their IT and security services offering.  Hitachi is now suited to address customers needing Identity and Asset Management solutions with full product line solution from a single provider.  This software was a needed addition to the wide variety of access control products including RFID and biometrics. The Hitachi ID software solution is currently implemented at over 200,000 users and supports single-core, multi-core and distributed processing environments.  One of the key applications is for SOX compliance reporting and access.

From a hardware perspective, there were lots of FPGA solutions for encryption/decryption of the data streams and authentication for access control.  Typical of the offering is the 10Gb AES softmacro for the Xilinix family of products that is available from Algotronix Ltd.  The IP is being offered on a 60 day/5 FPGA trial basis.  The predominant ID system for access control is still the hardware dongle with either a fixed or changing key.  Biometric ID (thumb, fingerprint, eye scan) were all still present, but were not highlighted as prominently as the software system for backing them up.  Hitachi was displaying their new finger vein scanner which is supposed to be more unique and consistently identifiable than fingerprint scanning.

One area that the software suppliers did not indicate they were addressing is the area of malware, viruses, and software intrusion in multi-core and GPU executable environments.  Shared cache systems attached to multiple core processors that also reference a single memory store have some issues with false flag generation for access control and ID confirmation applications.  At this time, none of the vendors that were asked about this problem had a definitive position on how it was addressing this problem for code installations on legacy software that was created for single core engines.
pc

The Synopsys User Group held it San Jose event recently. The opening keynote and introduction by Aart de Geus gave the direction for products for the coming year. The talk reviewed the standard speed up of PrimeTime, VCS, ICC, verification and litho sim. These improvement were made in part to support the large shift in the semiconductor community from an IDM model to a fab lite model.

The theme of the conference was the addressing of power usage/reduction as a driving design constraint and multi-power design. A number of the power issues are being addressed by the UPF group that is part of Accellera. Accellera group is also launching a VMM consortium to promote the use and creation of open VMMmodels. The new group is called the VMM Catalyst Program and absent from its current membership are Mentor, Cadence and Magma.

With the smaller process geometries (65nm and below) requiring a reworking of device level design for library elements, Synopsys introduced some major updates of the thier custom device environment. Their device simulators (HSPICE and others) are in the process of being recoded from single processor to multi-core awareness. They also rolled out a new repackaging and reshaping of the one of the old Avanti custom design tools (Cosmos) and have updated it ti work with OA. This new tool is called Orion, and includes schematic capture and custom device generation in addition to full custom layout. They did not memtion an OA to milkiway tramsition for the tool, so the assumption is that it is an OA tool only, and hence is not addressing any historic Analog Artist Applications or designs.

The EDA community and Synopsys interestingly noted that the new processes are driving designers back to device level design. As happens every couple of years, it is “analog’s time” again. The reality is, it may very well be the time that “analog” and device level primitive design is needed, however there are no innovations in tool flows or even new points tools being made in the custom design sector. Simply improving the throughput of an existing tool without a new flow to bring data in or improve the interpretation of result, does not rr real;y fix anything. As a results, the device level simulation at Synopsis is the same but faster than last year.

Once again the PR folks showed their high levels of paranoia by restricting the press to only a few sessions rather than inviting them to the whole event, this leaves the press continuing to hear from only disgruntled users.

pc

Yes, I’m still among the living.

I’ll be attending NAB next week for Chip Design magazine. Let me know if you want to meet at the show.

This years DAC is showing a lot of tools in device level and custom design tools and directions this year. In past years the show has been focusing on SOC, synthesis and P&R. For the new processes, the focus has shifted back to the building blocks - devices, component level physical design, DFM/DFY and power.

The quick one to get out of the way for discussion is power. The big showdown on the show floor between CPF and UPF which was rumored to be aiming to split all the fabs and EDA tool vendors into two camps is not really turning out that way. The actuality on the results is that both have customers using them for designs. Even though the two sides are shouting about who has the biggest numbers, the real decision will be made in the semiconductor customers playing field. As the technology for these two standards are based on implementing known good design techniques that have been historically done manually, the winning solution is most likely be chosen on a chip by chip basis depending on the selection of which mix of power solutions are needed, and how much automation/validation is required for the individual design. There is no real war, just engineering work to be done, and most of the people have better things to do than discuss it.

A lot of the tool vendors in this space actually had good products that appear to be on the right track for the answer (their presentations/booths all had the same foil that showed how they uniquely supported the full set of known power reduction solutions that was invented and used since mid 70’s). In various and multiple parts of the flow for solutions are ArchPro, Sequence, Synopsys, and a whole gang of others that can be found on the lists from the CPF and UPF camps. Once dad gets home from work, and can stop the two kids from fighting by giving them timeouts and sending them to their respective rooms to calm down, the sector should be very effective for the designers.

A big area at the show was the prominence of statistical design. In addition to the traditional big players showing products in the area, there were some small companies showing products that covered a large range of design. These included, but is not limited to, Extreme DA - STA , Solido Design - device level design, and Nanno Solutions - interconnect design.

Other non-front end design tools providers were at the show displaying pretty stable code that supports manufacturing data for variation. This was classified as the DFM/DFY/DF(letter of choice this week to try and present a market differentiation) players who provide business models in the form of tools, services, flow partners and the combo value meal ( but without the large fries, as the sector is health conscious and trying to stay alive). Companies showing in this space included Ponte; Clear Shape; PDF Solutions; Anchor Semiconductor; Blaze DFM; Brion; the big 3 - C, S & M; Magma, SiliconCanvas and probably others. The big guys are all known and positioned in this space, and really don’t need any more discussion, the fabs who are providing processing with the “approved” vs “recommended” tool lists for sign off is all the info any designer needs.

Their were two other players in this area who showed a different spin on the answer - (1) Sagantec, a long time player in the EDA sector, has a DFM fixing/repair tool as they are able to successfully leverage thier compactor/edge mover technology to automatically* repair polygon level problems identified by the tools in the list of Dfx tools (* technology file, context aware rule set, and batteries not included). (2) SoftJin who provides custom software modules for DFM, data translation and manipulation, and most other physical design and synthesis level design subroutines to EDA companies, IDM and Fabless with their own CAD depts and recently Fabs with thier own CAD depts. This is good for the industry, as a lot of the companies are all calling the same “engine” subroutine from their integration kits, we are slowing be relieved of having to see hundreds of pointless benchmark slides and we can have confidence in the accuracy of the answers from the new suppliers as they are all using a common code base inside different bright and shiny wrappers.

It appears, the design world has realized that custom libraries and multiple views are a reality even in a world of licensable IP. This brought out a number of players covering the sector of library creation, characterization and view comparison. Folks in this space are Nangate - Lib creation, characterization and comparison; Fenix DA - view comparison; Altos Design - Characterization, and finally long time market entrants Simucad and Library Technologies who both provide the industry baseline products. There are probably more in this space, the others have their products are part of solution families are not actively promoting them as “point tools” but as part of a large SOC completion picture. The folks at ChipEstimate.com and Design Reuse are continuing to do a good job of providing the industry with an on-line shop and compare feature for licensable IP. As this is a required step for current SOCs, the two companies have done well keeping up with the huge and growing lists as well as providing higher level tools that allow for engineering level comparisons of the offerings, not just lists of existence.

The last area of the show that was showing new stuff for the custom design world was the simulation space. SPICE, RF and AMS simulation are now part of the mainstream flows, so the longtime under appreciated tools are getting the visibility they deserve. These include the two industry standards Synopsys HSPICE and Simucad’s SmartSpice, followed by Berkeley Design Automation, Dolphin Integration, AWR, Ansoft, Agilent, Cadence, Xoomsys, Nascentric, Legend Design Technology, Lynguent, and Mentor.

The SPIE/BACUS Photomask technology conference in Monterey, CA, was very lively this year. Along with the traditional long time faithful attendees, there were a large number of new faces from the EDA-DFM community as well as folks who used to attend the now defunct Advanced Reticle Symposium (ARS).

The conference had it share of imaging, illumination, photoresists, films and substrate materials, repair and inspection papers. A good number of the papers however followed a new trend of DFM, OPC, RET, methodology, tools and design intent validation content. Surprisingly, these papers were being presented by all three sides of the issue – semiconductor companies, wafer/mask fabs and tool providers.

Some of the highlights from conference that seem to directly be of interest to the design community were:

Saratoga Data Systems, which has GDSII file size reducer and a high speed FTP tool. The GDSII product is interesting as it is not a “compression” format where data validation is required to make sure the new file can be “restored” properly, but actuall a reorganization of the eixisting file which makes it not only smaller but still directly usable in the reduced form. They also have introduced a very high FTP protocol that results in many multiples faster data transfer – so remote design teams with centralized server farms running physical verification and MDP/OPC/etc is now actually practical.Soft Jin had poster session about their new distributed “engine” tools that support smart distribution of a core EDA engine (simulation, verification, etc) on multiple machines in a net. One of the cool things about it (that may also limit it’s use) is the fact that to get the performance, the designers have to actually partition and build their designs properly with hierarchy and not create a huge flat blob. Maybe with the performance enhancement that is available with this technology, the RTL designs and P&R engineers will finally follow the rule and do things right.

An interesting poster paper was presented regarding everyone’s favorite topic – ESD. This time, however the issue is not the IC’s but the Masks and the associated carriers. At only 5X images of 65nm and 45nm geometries, ESD strikes that come in the wafer fab line happen on “good” masks, after mask inspection and can destroy real data on the plates. The folks at AMTC reported test results on various carrier materials including some exotic carbon nanotube products to try and reduce this issue. According to Pozzetta Products and Gudeng Precision both suppliers of the reticle carriers, this is one of the top 3 issues brought to their attention by wafer fabs and masks fab world wide.

The big guys – Mentor, Cadence, Synopsys – all had new product roll outs that were shown at the conference and results presented from REAL manufacturing partners and wafer results from fabs and semiconductor companies. I guess the real data and results get saved for the technical conferences, so at DAC we are going to have continue to live off the many bright colors from the product slicks to keep us happy. Cadence , Mentor and Synopsys all have very functional products and results at the show, it is pretty amazing how the practicality of their offerings have non-overlapping results and uses even though the products names are all the same.

As a last highlight – the business side showed continued revenue growth in the mask sector, while the number of units is still stuck at about 700,000/year. The split includes >50% at 0.25um (250nm) or larger and about 2% at 65nm or below. – pc