Archive for May, 2012

May 28 2012

New Designs Focus on Devices

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In the midst of big chip announcements (Intel’s IvyBridge at 22nm, Nvidia’s Kepler at 7B devices) the discussion has centered on techniques for managing the design of these very large chips. On topic that has not been highlighted, but is apparent in the industry is the resurgence on basic devices and device level circuit design.

With the rise of restricted design rules, there is also a rise in restricted device design. This means the is a higher reliance on differentiation of the circuit function and performance though design architecture and device topology rather than just “throwing gates at it”. These new design blocks are setting new levels of power/performance.

The new circuits are not just on logic gates, they are analog blocks and memories also. Flash is shifting from SLC to MLC and now a TLC structure. This is requiring new sense amp topologies and performance to accompany the new cells. The new analog blocks are allowing RF to implemented in CMOS using the same die as digital functions.

This rise in device level design is different from the 60′s-90′s which focused on single blocks with small device counts due to the limitations in device simulation. New high capacity device simulators and the use of multi-threaded and distributed computing now allow for full functions and subsystems to be simulated at the device level, and perform optimization. These tools are well suited to statistical design methods, as is the design techniques for device level design. These new tools are one of the fastest growing areas of the EDA community, and are forging a tight relationship with the process development and operations groups.

The emphasis on device level, or bottom up design methodologies, works well up to the macro cell and mega cell level. At this point, the blocks meet top down design methods that are focused on data, I/O and bus architecture. This combination works well for advanced process technologies, however it requires a more traditional chip design skill than is available from the recent trend of “C and C++ programmers” who are creating chip designs.

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