Archive for March, 2012

Mar 09 2012

ISQED2012 Expands with Co-located Events

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The 2012 ISQED (International Symposium on Quality Electronic Design) is expanding this year to include two co-located events at the Techmart in Santa Clara on Monday 3/19 and Wed 3/21 of the three day conference. While the main program has continued to focus on the the quality of design in both the systems and process space, it is increasingly covering tools, IP blocks, SOCs and full electronic systems. There is a migration of topics to include process and manufacturing interactions with the electronics. .

The conference schedule includes multiple sessions on power aware design, energy efficient design, 3D packaging and analysis, and system level failure & test methods. The plenary talks by Cadence, GlobalFoundries and UCSD focus on advanced node processing & design, IMEC is speaking on Variability, Aix-Marseille Univ on the topic of Resistive Memories and Texas Instrument son the topic of Analog Innovation. Synopsys will be presenting a retrospective talk on the trends on the collaboration between the Space Program and the electronics industry.

The co-located events are covering the expanding ecosystem of the system design community – education and sensors. They are the Interdisciplinary Engineering Design Education Conference (IEDEC), now in its second year, and SensorsCon. Engineering education has to change from the traditional non-interacting silos to be able to take advantage of skills in multiple programs to solve current and emerging problems. With this concept in mind, the IEDEC event, being held Monday 3/19, is focused on multi-skill and multi-subject course work that better fits todays engineering realities. It discusses coursework, programs and curricula for crossing the traditional engineering school vertical tracks. The program is highlighted with presentations from AMD on hardware/software co-design with OpenCL, TE Connectivity on incorporation of hardware/software/social engineering and data mining for digital signage, CSNE Albany on the creation of an ABET approved Nanotechnology degree program, and UCBerkeley’s CITRIS program on the role of Computing on Interdisciplinary Data.

SensorsCon was developed to address the rise of the Internet of Things (IOT). IOT and mobile devices have brought Sensors to the forefront of the electronic system universe. The event is being held Wed 3/21 at Techmart and addresses the non-standard devices, that brings a number of challenges and reliability issues to the system design arena. Industry MEMS pioneer Janusz Bryzek from, Fairchild Semiconductor, Bosch, Intel, Dust Networks, Sensors Platforms, Sprint, Mphasis, California Polytech and Microlytica, will be presenting on the manufacturing, design and implementation of building high reliability consumer and industrial products that incorporate a Sensor base.

Registration for all conferences, being held at TechMart in Santa Clara,CA, is open now.

 

 

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Mar 01 2012

DRAM updates at ISSCC 2012

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At the recent ISSCC, the DRAM rollouts took place opposite of the microprocessor announcements. The well attended session was greeted with several themes – new interface and performance, lower power, higher densities, and new processes.

The new 3.5Gbps DDR4 SDRAMs were introduced by Samsung. Not only is the interface faster, but it brings new levels of error correction and tolerance through an improved signaling method. Hynix also introduced a DDR4 SDRAM product that uses the lower 1.2v operating voltage, a x4 half page architecture and a reduced active bank current. These devices again not only focused on the speeds possible with the new interface, but the improved reliability and data integrity possible.

As these devices move through process technologies from 38nm through 20nm, device and signally reliabilty with the lower operating voltage was the driver. Architecture changes, sense amp, cell and read/write cycle changes have to be implemented to support the needs of the 1.2v power supply for high speed server memory. For mobile applications, the speed is not as critical as the power and the reliabliy. UCLA presented a mobile memory interface with a power factor of 4pJ/pin that supports a 5Gbps BaseBand and 3Gbps RF band data rate while maintainng a BER of 10-12.

The session then moved to process technologies. Higher densities and performance were achieved with TSVs as a method for addressing leakage current for power reduction. In addition to TSVs, new memory technoligies in the form of Phase Change were shown. Samsung displated a 20nm 8Gb PRAM that operates at 1.8v and was able to support a 40Mb/s write throughput. This was a significant density, performance and power improvement of prior work.

These papers represent the shift in enterprise and mobile DRAM from density as the key driver to power and reliability as the #1 and #2 application targets. Just like processors, there is more the memory market than cheaper/higher density, making sure they work is now the key.

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