Archive for January, 2012

Jan 16 2012

Interfaces dominate CES IP

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At the 2012 CES conference, there were many IP providers mixed in amongst the many end product companies. These IP providers were showing capabilities as a well as ASSP products targeting the mobile community and handheld products.

The core controller IP providers – Tensilica, ARM, Imagination Technologies and MIPS were all showing their latest scalable blocks targeting higher performance graphics, sound and battery lifetime. These blocks were supported not only be new SDKs but also in reference designs that appeared as early product from the major systems providers.

A change this year was the large number of IP blocks that were incorporated in ASSPs that were shown. Companies such as Nvidia, Broadcom, Samsung, Qualcomm and Marvell were showing thier own versions of these IP blocks, now configured as systems under the larger scope of an architectural licence for these core processors.

Peripherals and interfaces were not left out at the show. The Qi group (Wireless Power Consortium), USB IF, WiSA and Wireless HD, HDMI and Display Port groups had multiple vendors showing both IP and systems/block level solutions. The data rates moved up at the show and most people had the new standards – SATA 3 (6Gbps), USB 3.0 (5Gbps), Thunderbolt (up to 10Gpbs), Display Port 1.3 (5Gbps) in thier products. This has changed the technology node to being 90nm as the largest process size, as the SERDES at this node and below can handle the high speed data in a straight forward manner.

A couple of surprises in the IP is the large number of blocks that stayed at the 1.8v power rails, and did not scale to 1.3v or below. While beneficial for the core logic and state machine portion of the design, the power level has proven to be quite challenging to interface blocks and anything driving large capacitive loads such as cables or connectors.

The FPGA providers were focusing their IP and solutions on the high end display (multiple TV models) and the automotive marketplace. These are both aggregation points for multiple technologies and multiple data bus formats. As a result, the flexibility of the FPGAs logic to be adjusted on a per model basis while providing sub 3Xnm process and performance access is the major driver for the UHD displays and advanced Driver Assist and Automotive Infortainment systems that were shown.

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