Nov 08 2011
Update on Nano-Photonics
The IEEE Nanotechnology Council is holding a half day seminar on photonics on Tues Nov 15 in Santa Clara. (info at http://www.ieee.org.nano) The area of photonics is quite varied these days and the program is addressing 4 key areas of the technology.
Opening speaker Dr. Hughes Matras from CEA Leti (Grenoble, FR) will be discussing 3D ICs and chip-to-chip photonics interconnects. They will be presenting results and goals for thier ongoing research in the space. These parts are targeted for both Si based photonic circuits – logic to logic and logic to memory.
The second speaker is Dr. Chanming Su of Bruker-Nano. Dr. Su has create a fast scan Atomic Force Microscope which now enables single digit nanometer resolution metrology at practical quality assurance and debug speeds. One of the major challenges of nanotechnology is the imaging of the geometries in question. A second challenge is to verify that these sub-resolution features and the resulting devices are created properly. The presentation will review the technology behind the Fast Scan AFM as well as capabilities of the tool in production use.
The next speaker will be Dr. Hakaru Mizoguchi of Gigaphoton. He will be discussion the advances in EVU lithography through their development of a new high power EUV source. The new source is based on an ionization system for the liquid Sn droplet atomizier. The final speaker is Dr. Xiang Zhang of UCB. He will be presenting on solid state lasers and limits on diffraction grading and other optical elements in solid state light paths. These products are a critical part of high speed communication.
After the speakers presentation, Ed Sperling of Semiconductor Manufacturing & Design (www.semimd.com) will lead the panelists in a discussion of future directions and challenges in integrated photonics and the process technologies they will be using. Registration for the event is available on-line at www.ieee.org/nano and admission is also available at the door for the event. The event is being held at the Texas Instruments Conference Center in Santa Clara. The center was formally the National Semiconductor Conference Center and runs from 12noon – 5pm on 11/15. Lunch is included and parking is free.