Archive for October, 2011

Oct 29 2011

ARM Highlights Power and Processors

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The 2011 ARM Techcon was well attended and busy this year. The technical sessions were rightfully quite packed as the topics being presented by ARM and it is many partners was low on product advertising and high on technical content – a rarity for many of today’s events. The conference addresses a diverse client base – IP creators/providers, SOC developers, FPGA users that integrate the cores, and systems designers that use both custom and standard products that incorporate the ARM cores. In past years, the communities were tightly integrated, this years event, chose to separate the two groups (chips and systems) segregating the “chip” folks to the “kids table and being out of sight/sound of the adults” and the “systems” folks to the “grown ups” who got the “big table in the main room”.

The challenge that results, is that attendees who are doing SOC design for a specific application, now need to attend all three days, but two of the days do not discuss the context of the architecture, test, programming and performance optimization that reviewed on the Systems days, The attendees building systems now also have to attend all three days to get the technology overviews, low power techniques, reliability and interface details from the chip day to understand how to take advantage of these features in their FPGA and board level implementations.

There were a number of design tradeoff sessions that had new design solutions such as the SiTime MEMS resonator which in addition to being a stacked die integratable solution, also allows for the elimination of PLLs in the SOC design and the timing issues associated with the jitter in traditional PLL based clock distribution designs. This is becoming more critical as additional sensors are being used in these multi-core systems, so temperature compensation and data converter stability have increased impact on the overall performance. The results are fsec jitter levels on a 100Mhz clock.

The systems day included an overview of ARM itself and had a nice tradeoff comparison of the ARM vs Cortex processors, and the 16, 32 and 64 bit instruction sets, applications, and programing requirements for the various applications. This discussion included the multi-core architectures and pipeline designs of these cores and the associated AMBA system IP / Mali Media IP.

An overall theme was that the ARM IP was designed for minimizing power consumption while providing the highest performance/power ratio in the industry. This has allowed the IP to be used in literally Billions of end products shipped, since the company was formed in 1990. The product line was shown to be addressing the shift in market need from simple control of an application to being a main compute processor for mobile multi-media data consumption.


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Oct 21 2011

Power Architecture turns 20

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In a recent discussion with Fawzi Behmann, we reviewed the state of the Power Architecture, which is now in its 20th year. The processor was started as reasearch in 1977, and then became a a standalone product (the 68000 processor) in 1979. The Power Architecture was put into SoCs in the early 1990′s and was introduced as a multicore with virtualization architecture in 2001. The current version of the processor – the Power7 is the compute engine behind the IBM Power7-Blue Water HPC and the Blue Gene / Q. The group put together the Power ISA in 2005 that created a spec for the product and specified the supply chain. In 2010, they released version 2.06B of the spec, which dealt with multicore, virtualization, energy management and reliability of the design and cores. The core is now able to take advantage of new operating systems and appellations thanks to new SDKs that have been developed. They are moving to run OpenCL and Android has been ported to PowerPC along with the other platforms. This allows for embedded applications to get an optimized OS, and the code is available in source form, and proprietary kernals can be developed. The graphic that follows shows the current roadmap for processors and cores.

Power Architecture Roadmap

One of the new applications of the part which has dominated space use, medical instruments and automotive, telecom, compute/analytic applications is natural language processing. This is not the same as the regular expression processing for policy decisions, rather, it is targeted at health care and medical record processing. The engine can process upwards of 200M pages/sec of EHR. These new applications are starting to take advantage of the transactional memory design in the Power7 which is optimized for multi-core processing. The SoC design for the cores is a hardware/software co-design function. The designs are captured using Rational. And then a flow (as shown in the following figure) is used to create the design using EDA tools from Synopsys, Cadence and Mentor for the hardware design. The design is a true 64 bit with full 32 bit subsets.

Hardware/Software Collaborative Development

To enable new development and increase embedded applications, has worked to simplify the licensing of the technology. The license model now includes: IBM Power Architecture Licensing Program – Lowering Barrier for Developers (a) “No-barriers” license for Power 405 (no standard access fee) (b) Multi-use agreement for Power 405, 460 and 470 for 5-years (c) Synopsys University program for Power 405 member access for new applications (d) VAR agreement with C*Core. These licenses have additional provisions for China and as a result they are experiencing high growth in multiple markets.

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