Archive for September, 2011

Sep 24 2011

Energy Efficient Electronic Systems at UC Berkeley

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On Nov 3 & 4, 2011, the Center for E3S of  the EECS department is holding their second annual conference at the UC Berkeley campus.  This year’s event spans 2 days and has 19 confirmed speakers following a keynote to be presented by Dan Hutcheson of VLSI Research Inc .  This years symposium will cover a range of topics including:

Low voltage tunneling FETs;
Low voltage nanomechanical logic;
Energy efficient spintronic logic;
Energy efficient memory and storage devices;
Energy efficient chip scale interconnects; and
Low voltage CMOS circuits and architectures.

The center’s chair Dr. Eli  Yablonovitch will be speaking and showing off research activities in the group.  The center is focusing on the challenges of lowering the operating voltage of electronics and electronic systems and addressing the growing power that is being consumed by the aggregated IT infrastruture and connectivity that is pervasive in today’s society.  The E3S Center is responding to the challenge under the following charter:

“The Center for Energy Efficient Electronics Science (E3S) has been established to:

  • Open a new energy efficiency frontier in information technology by developing transformative science and technology that reduce energy consumption in electronic systems by orders of magnitude.
  • Inspire and train a diverse generation of scientists, engineers, and technicians that applies this new science and technology to benefit society.”

based on the quality and diversity of speakers, this events is shaping up to be the premier low power event on the west coast this year.  Information on the conference and registration is available at:

http://www.e3s-center.org/events/11/sym2011-home.htm/

 

Discounted early registration is available on the site through October 7.

PC

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Sep 22 2011

TrueMask DS: Mask-Wafer Double Simulation Platform

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At the 2011 SPIE masking conference, known as BACUS, we had a chance to meet with and talk to Aki Fujimura of D2S, Inc about his company’s new product offering. The new platform is an interactive masking workstation that allows for simultaneous optimization of lithographic patterning for BOTH mask and the resulting wafer image.

The integrated software / workstation platform was created to address the discontinuity that has arrived at the sub-80nm (on mask feature size) / sub-20nm (on wafer feature size) nodes.The system works by having mask designers target highly critical areas and/or highly repetitive patterns up to 300umX300um (on mask). TrueMask DS allows the user to interactively trade-off the mask shot count and mask manufacturing margin with wafer manufacturing margin down to a resolution of 0.1nm on mask. The system also features Litho aerial simulation which helps feed the reduced interpretation time from running the 5umx5um (on wafer) object analysis. The graphic shows screen images that result from the various types of simulation.

Modeling results from TrueMask Mask-Wafer Double Simulation

The system helps bend the curve on mask costs. As current multi-million dollar mask cost explode due to multiple patterning and the need for complex shapes, this model based approach is targeting up to 25% cost savings for processing the shape set that is anticipated for the 15nm and below nodes. There is a corresponding shortening of the schedule along with the cost savings for the materials. As the system support eBeam sources, the system can simulate rectilinear, overlapping and in the future, variable shaped beam sources.

At 20nm feature size, the amount of OPC (Optical Pattern Correction) and SRF (Sub-Resolution Features) that is required to correctly represent the layout feature is very high. The features require many complex mask shapes, which may not be repeated based on context over large reach areas. The tool set reads GDSII and OASIS data and can interface with SEM for inspection of both mask and wafer patterns.

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