Archive for March, 2011

Mar 28 2011

Synopsys Litho and Manufacturing -SPIE Adv Litho 2011

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At the SPIE Advanced Lithography event in San Jose, Synopsys presented their current mask making solutions.  The solutions include : (A) Proteus Litho tool (OPC & LRC) for mask synthesis, (B) CATS for mask write, fracture, inspection and metrology,( C) Sentaurus for process and device TCAD, (D) Yield Expolrer/Odyssey which is a design centric yield managment tool and (E) LightTools/CodeV for optical design and analysis.  At the litho event the concentration was on the Proteus tools and the link between stages.
The delays in EUV have forced the current litho equipment to push past the 28nm node to the 20nm production nodes with the use of complex techniques such as double, triple and quad patterning.   The first use of limtited funtion EUV is now targeted for the 16/15nm node and wil require new corrections alogorithms and run time solutions.  For EUV one of the major changes is the writing of full reticles not jsut single fiels.  This changes the methodology and strategies for RETs such as DPT and MBAF (model based assist features) and how thet are put into the design.  At 16/nm the RET sequnce will include RBOPC, MBP{C, RBAF, SMO, MBAF, LELE, IMT, Spacer, LRE, and MEC for a supplement to the ArF Wet/EUV/eBDW litho flow.
The Proteus double patterning tool (DPT) solution delivers a design based compliance solutions to avoid zero yield masks, a cost based solver to minimize pinching and bridging, symmetry enforcement for better runtime and color balancing for uniformity between the two masks.  These solutions are part of a full flow for design that includes DPT awareness in placement, routing, compliance checking and fixing, creation of compliant GDSII, and DPT compliant fracture.
A major new feature of Proteus is the support Long Range Effect (LRE) for use with EUV.  These include mask shadow modeling and 3D compact models for improved accuracy and tunable short range flare parameters.  These models and the tool runs on standard x86 hardware and support pipelining on all steps. The prodcuts are currently available.

At the SPIE Advanced Lithography event in San Jose, Synopsys presented their current mask making solutions.  The solutions include : (A) Proteus Litho tool (OPC & LRC) for mask synthesis, (B) CATS for mask write, fracture, inspection and metrology,( C) Sentaurus for process and device TCAD, (D) Yield Expolrer/Odyssey which is a design centric yield managment tool and (E) LightTools/CodeV for optical design and analysis.  At the litho event the concentration was on the Proteus tools and the link between stages.

The delays in EUV have forced the current litho equipment to push past the 28nm node to the 20nm production nodes with the use of complex techniques such as double, triple and quad patterning.   The first use of limtited funtion EUV is now targeted for the 16/15nm node and wil require new corrections alogorithms and run time solutions.  For EUV one of the major changes is the writing of full reticles not jsut single fiels.  This changes the methodology and strategies for RETs such as DPT and MBAF (model based assist features) and how thet are put into the design.  At 16/nm the RET sequnce will include RBOPC, MBP{C, RBAF, SMO, MBAF, LELE, IMT, Spacer, LRE, and MEC for a supplement to the ArF Wet/EUV/eBDW litho flow.

The Proteus double patterning tool (DPT) solution delivers a design based compliance solutions to avoid zero yield masks, a cost based solver to minimize pinching and bridging, symmetry enforcement for better runtime and color balancing for uniformity between the two masks.  These solutions are part of a full flow for design that includes DPT awareness in placement, routing, compliance checking and fixing, creation of compliant GDSII, and DPT compliant fracture.

A major new feature of Proteus is the support Long Range Effect (LRE) for use with EUV.  These include mask shadow modeling and 3D compact models for improved accuracy and tunable short range flare parameters.  These models and the tool runs on standard x86 hardware and support pipelining on all steps. The prodcuts are currently available.

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Mar 22 2011

Expanding applications and systems -ISQED 2011

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March 15, 2011 – Santa Clara, CA – The 12th annual ISQED conference (www.isqed.org) kicked off with the themes of next generation systems and applications.  The keynote “Multitechnology Hyperintegration Platform: the technology crystal ball” by Dr. Kamran Eshraghian was very engaging and well received by the early morning audience.  His discussion focused on the creation of disruptive technologies based on the SoS or System on System space.  The innovation gestation period was shown by example to be about 30-50years from creation of the concept.  This was illustrated under the timeline for the Memristor – it was theorized in 1971 and then realized in 2008, its manufacturability and integration into products is still on-going and is expeced to hit its peak in the 2020′s.
On a similar schedule, the new area of amibient intelligence – or pervasive computing and
connectivity was launched in 1987 and should see initial realization in 2020, with production in 2030′s.  Another area of discussion was the creation and use of metamaterials.  These are materials with non-standard characteristics since as a negative k factor for optics.  These materials, as well as the continuing shrinking of micro designs to nano designs, will result in new interactive systems and sensors that will be largly photonic based.  Dr. Eshraghian discussed how we currently don’t have a crystal ball to show how these pieces come together, but the direction is that the technology, once mature, does make its way into the nominal consumer culture on a global basis.
On the following technology progress line, the next speaker was Dr. Fabian Pease.  His topic of discussion was “For how much longer can Moore’s Law hold?”.  His discussion focused on the actual drivers from the current technology node, and made the argument it is NOT the transistors, it is the wiring that is in the scaling equation.  The key to Moore’s law is the lithography scaling in both geometry and cost.  The 500x increase in the cost of the litho equipment is directly proportional to the 500x decrease in the cost of minimum sized devices in the process.  To make the next transistion, something radical has to happen.
In his discussion, he indicated the most significant advance in process technology since the start of the CMOS era, is the application and development of Chemical Mechanical Polishing (CMP).    The next area of development to help maintain the density scaling is to move away from the confinement of a single plane technology.  3D technology and multi-technology stacking will help push the scaling for another several decades and will help remove the direct cost proportionality with the cost of litho. In the 3D world, the mixed technology allows for functions  to be implemented with both high and low litho cost processes, that can meet the scaling rules for functionality and not exceed the cost constraints that are needed for high volume use.
The second day of the conference, Robert Patti of Tezzaron Semiconductor, gave an overview of 3D stacking technology, and their wafer bonding technology.  The method they have developed and licensed to many major semiconductor companies, is based on face to face landing pad bonding of two designs – typically processors to memory, and can contain billions of vertical connections per 300mm wafer.  The discussed the reliability of the bonds, and that thier methodology requires the application to create the test methodology based on post assembly test.  They do not run tested die on the wafer, as it introduces mechanical damage to the wafers,, instead they rely on PCM tested wafers.
PC

March 15, 2011 – Santa Clara, CA – The 12th annual ISQED conference (www.isqed.org) kicked off with the themes of next generation systems and applications.  The keynote “Multitechnology Hyperintegration Platform: the technology crystal ball” by Dr. Kamran Eshraghian was very engaging and well received by the early morning audience.  His discussion focused on the creation of disruptive technologies based on the SoS or System on System space.  The innovation gestation period was shown by example to be about 30-50years from creation of the concept.  This was illustrated under the timeline for the Memristor – it was theorized in 1971 and then realized in 2008, its manufacturability and integration into products is still on-going and is expeced to hit its peak in the 2020′s.

On a similar schedule, the new area of amibient intelligence – or pervasive computing and connectivity was launched in 1987 and should see initial realization in 2020, with production in 2030′s.  Another area of discussion was the creation and use of metamaterials.  These are materials with non-standard characteristics since as a negative k factor for optics.  These materials, as well as the continuing shrinking of micro designs to nano designs, will result in new interactive systems and sensors that will be largly photonic based.  Dr. Eshraghian discussed how we currently don’t have a crystal ball to show how these pieces come together, but the direction is that the technology, once mature, does make its way into the nominal consumer culture on a global basis.

On the following technology progress line, the next speaker was Dr. Fabian Pease.  His topic of discussion was “For how much longer can Moore’s Law hold?”.  His discussion focused on the actual drivers from the current technology node, and made the argument it is NOT the transistors, it is the wiring that is in the scaling equation.  The key to Moore’s law is the lithography scaling in both geometry and cost.  The 500x increase in the cost of the litho equipment is directly proportional to the 500x decrease in the cost of minimum sized devices in the process.  To make the next transistion, something radical has to happen.

In his discussion, he indicated the most significant advance in process technology since the start of the CMOS era, is the application and development of Chemical Mechanical Polishing (CMP).    The next area of development to help maintain the density scaling is to move away from the confinement of a single plane technology.  3D technology and multi-technology stacking will help push the scaling for another several decades and will help remove the direct cost proportionality with the cost of litho. In the 3D world, the mixed technology allows for functions  to be implemented with both high and low litho cost processes, that can meet the scaling rules for functionality and not exceed the cost constraints that are needed for high volume use.

The second day of the conference, Robert Patti of Tezzaron Semiconductor, gave an overview of 3D stacking technology, and their wafer bonding technology.  The method they have developed and licensed to many major semiconductor companies, is based on face to face landing pad bonding of two designs – typically processors to memory, and can contain billions of vertical connections per 300mm wafer.  The discussed the reliability of the bonds, and that thier methodology requires the application to create the test methodology based on post assembly test.  They do not run tested die on the wafer, as it introduces mechanical damage to the wafers,, instead they rely on PCM tested wafers.

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Mar 08 2011

ISQED 2011 – highlight on low power & education

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In its 12th year, the ISQED Conference is driving the forefront of QOE, QOR, QED and the methodology behind meeting those goals.  This years event (March 14-16 at the Hyatt in Santa Clara) features 13 tutorials, 7 keynotes, 21 session tracks, poster sessions and exhibits.  The conference has shifted the content of the event to include more discussions and papers on system level design, SOCs, FPGAs and testability/verification which are now critical functions to the user experience of the electronic prodcuts.

The tutorials topics include:

* SRAM and Logic Circuit Techniques for Low Power Design in 32nm and Below
* Automated Design and Porting of Analog/Mixed-signal Circuits
* Current and Electric Field Induced Switching of Ferromagnets for Low-power Memory Applications
* Application of Spintronics for MRAM and Memristor-based Computing
* Hybrid Electrical Energy Storage Systems
* System Level Power Management for Cellular Chipsets
* Modeling, Abstraction, and Verification of Industrial Flash Memories
* TechTuning : DFM Methodology for Stress Management for 3D TSV Products
* Stress Assessment for 3D IC performance: Full chip analysis
* TCAD Simulation for Stress Management in 3D IC
* Multi-scale materials characterization – Input for stress simulation and model validation
* Verification of Power Managed Wireless SoCs

Keynotes for the event include speakers from  Cadence Design Systems, Innovation Labs, Stanford University, Synopsys, Tezzaron Semiconductor, Marvell Semiconductor, and Mentor Graphics.  he topics range from smart meter to 3D assembly to the future of Moore’s Law.

Registration for the full conference and tutorials is still open.  There is free registration for the exhibits/poster sessions and the co-located Electronics Design Education Conference which is held on Wed 3/16 at the event.

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