Archive for February, 2011

Feb 27 2011

Ethernet Summit – PHY & MAC drive the technology choice

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At the recent Ethernet Summit the theme was 40G and 100G – technologies that are here today.  With the large number of major semiconductor manufacturers adopting the 40nm low power process nodes, the number ot 40G and 100G system solutions are growing and being readily adopted in systems.
The standard architecture for a 40G system is to have 4 lanes of 10G at the front end.  The current incarnation of 100G is either 10 lanes of 10G or 8 lanes of 12.5G interfaces.  These are speed limited by the SERDES that create the L1 PHY that includes the transceiver.   At the 40nm node, these PHYs and SERDES can be creates with low power processes, yield well, support the lower operating voltage and be implemented in single, dual and quad SOCs.    The primary differentiation is whether the connection is made with fiber or with copper.  The standard wire specs are out and they have a lower cost of installation and per wireing but fiber has noise immunity and a cleaner signal over distance.
For increased data rates, the challenge of 25Gb channels were being discusesd for both 40nm and rebn processes.  The advent of these higher spead parts have driven up the complexity of the PHY.  The MAC is still segregated out to be revised and created seperately to support the faster movement snd revisions of the data formats and handshakes.
The discussions focused on components, cables, connector, test equipment and validation for the interfaces.  The key portion for these high speed channels is the design validation & the board level characterization.  The deployment and validation of the BER and ECC for these data rates is their key to use in the cloud server environment.
The system design for these blocks has to incorprate a validation ot the whole TCP-IP stack fron L0 (cables) through L1 (PHY) all the asy up to L7 which is applications.  The data center design – from the use of SSDs, where to implement PCIe cards, and howe to partition between CPU/GPU and SAN are now being directly related to to the selction of the PHY and MAC that bring the data to and between the racks.  These high speed applicaitons and the voracious appetite for data movment has once again restored these analog specialties to the critical path of network design.
PC

At the recent Ethernet Summit the theme was 40G and 100G – technologies that are here today.  With the large number of major semiconductor manufacturers adopting the 40nm low power process nodes, the number ot 40G and 100G system solutions are growing and being readily adopted in systems.

The standard architecture for a 40G system is to have 4 lanes of 10G at the front end.  The current incarnation of 100G is either 10 lanes of 10G or 8 lanes of 12.5G interfaces.  These are speed limited by the SERDES that create the L1 PHY that includes the transceiver.   At the 40nm node, these PHYs and SERDES can be creates with low power processes, yield well, support the lower operating voltage and be implemented in single, dual and quad SOCs.    The primary differentiation is whether the connection is made with fiber or with copper.  The standard wire specs are out and they have a lower cost of installation and per wireing but fiber has noise immunity and a cleaner signal over distance.

For increased data rates, the challenge of 25Gb channels were being discusesd for both 40nm and rebn processes.  The advent of these higher spead parts have driven up the complexity of the PHY.  The MAC is still segregated out to be revised and created seperately to support the faster movement snd revisions of the data formats and handshakes.

The discussions focused on components, cables, connector, test equipment and validation for the interfaces.  The key portion for these high speed channels is the design validation & the board level characterization.  The deployment and validation of the BER and ECC for these data rates is their key to use in the cloud server environment.

The system design for these blocks has to incorprate a validation ot the whole TCP-IP stack fron L0 (cables) through L1 (PHY) all the asy up to L7 which is applications.  The data center design – from the use of SSDs, where to implement PCIe cards, and howe to partition between CPU/GPU and SAN are now being directly related to to the selction of the PHY and MAC that bring the data to and between the racks.  These high speed applicaitons and the voracious appetite for data movment has once again restored these analog specialties to the critical path of network design.

PC

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Feb 21 2011

Healthy Living Electronics dominated by Power – ISSCC 2011 preview

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The theme for this years ISSCC (International Solid State Circuits Conference) is “Electronics for Healthy Living”.  In addition to the new microprocessors, memory and data converter technologies, the focus and keynotes are directed towards health care products.  The common theme between all the talks, are health care is being driven by mobility, information flow, and power.  The key to high quality data transfer is having enough power to complete it – either wired or wireless.  The key to mobility is to have autonomous power for the devices for the duration of time that it does not impact the activity the user is involved with.
The keynotes cover the range of silicon’s impact on the health care.  Medtronics is discussing the scope of implantable devices, the reliability, data transfer and the system architecture of the implanted and external portions of the system.  IMEC then follows with a discussion of the invasion of specialized purpose sensors that are now possible, their in-roads into health care and the creation and powering of body area networks.  Samsung then speaks on a different twist for health care.  Their discussion is that the major cause of pollution is energy consumption and hence generation.  The way to address this problem is through reducing energy use in the manufacturing process and in the design of devices that utilize less power and can take advantage of  innovative packaging.
Following the keynotes is the inaugural Plenary RoundTable discussion on how to address the next 10X reduction in power.  The discussion is is hosted by Jan Rabaey of UC Berkeley and features TSMC, Hitachi, STMicro, Infineon, IMEC and other senior experts from the semiconductor and university commnity.  This challenge, encompassing process innovation, CAD, design flows for digital, RF, analog, and memory is one of the key drivers for the next generation of energy efficient electronics.
Energy efficiency has now earned its own session with Energy Efficient Digital which will be detailing such projects as ultra-low-voltage standard cells that operate down to 62mv of supply.  Other new technologies include a 28nm DSP from TI that can operate at 0.6V, and wireless sensor processor that utilizes only 10pJ per clock cycle.
The technology development sessions once again mix between high performance and low power.  On the high performance side, architectural design for Terahertz (300GHz to 3THz) imagers and associated device blocks – amplifiers/antennas are being shown.  On the low power side , a transceiver that can operate at 0.24nJ/b, and energy scavenging converters now up to 72% efficient and generating 95mv will be presented.
Filling out the program are tutorials on Ultra-low power digital design and a forum on Ultr-low voltage VLSI for energy efficient ICs.  These sessions are expecting large attendence as they are the dominant directions for the next decade.
The shift for the conference and the industry is dramatic.  Historically – the past 40 yaers, the conference has been the platform for the biggest, and fastest semiconductors were debuted.  These devices are now having to share the spotlight with the smallest, highest density and lowest power devices.  The show is focusing a lot more on architecture, device technology and the systems aspects rather than just circuit blocks.  This focus accompanies the idea that SOCs are true systems, and the they need to be addressed as such with focus on function, performance,  power and application.  The body area network discussions and technology, which balance data transfer and power as the main tradeoffs, are representative fo the future of the systems and IC discussions in the future.
Pc

The theme for this years ISSCC (International Solid State Circuits Conference) is “Electronics for Healthy Living”.  In addition to the new microprocessors, memory and data converter technologies, the focus and keynotes are directed towards health care products.  The common theme between all the talks, are health care is being driven by mobility, information flow, and power.  The key to high quality data transfer is having enough power to complete it – either wired or wireless.  The key to mobility is to have autonomous power for the devices for the duration of time that it does not impact the activity the user is involved with.

The keynotes cover the range of silicon’s impact on the health care.  Medtronics is discussing the scope of implantable devices, the reliability, data transfer and the system architecture of the implanted and external portions of the system.  IMEC then follows with a discussion of the invasion of specialized purpose sensors that are now possible, their in-roads into health care and the creation and powering of body area networks.  Samsung then speaks on a different twist for health care.  Their discussion is that the major cause of pollution is energy consumption and hence generation.  The way to address this problem is through reducing energy use in the manufacturing process and in the design of devices that utilize less power and can take advantage of  innovative packaging.

Following the keynotes is the inaugural Plenary RoundTable discussion on how to address the next 10X reduction in power.  The discussion is is hosted by Jan Rabaey of UC Berkeley and features TSMC, Hitachi, STMicro, Infineon, IMEC and other senior experts from the semiconductor and university commnity.  This challenge, encompassing process innovation, CAD, design flows for digital, RF, analog, and memory is one of the key drivers for the next generation of energy efficient electronics.

Energy efficiency has now earned its own session with Energy Efficient Digital which will be detailing such projects as ultra-low-voltage standard cells that operate down to 62mv of supply.  Other new technologies include a 28nm DSP from TI that can operate at 0.6V, and wireless sensor processor that utilizes only 10pJ per clock cycle.

The technology development sessions once again mix between high performance and low power.  On the high performance side, architectural design for Terahertz (300GHz to 3THz) imagers and associated device blocks – amplifiers/antennas are being shown.  On the low power side , a transceiver that can operate at 0.24nJ/b, and energy scavenging converters now up to 72% efficient and generating 95mv will be presented.

Filling out the program are tutorials on Ultra-low power digital design and a forum on Ultr-low voltage VLSI for energy efficient ICs.  These sessions are expecting large attendence as they are the dominant directions for the next decade.

The shift for the conference and the industry is dramatic.  Historically – the past 40 yaers, the conference has been the platform for the biggest, and fastest semiconductors were debuted.  These devices are now having to share the spotlight with the smallest, highest density and lowest power devices.  The show is focusing a lot more on architecture, device technology and the systems aspects rather than just circuit blocks.  This focus accompanies the idea that SOCs are true systems, and the they need to be addressed as such with focus on function, performance,  power and application.  The body area network discussions and technology, which balance data transfer and power as the main tradeoffs, are representative fo the future of the systems and IC discussions in the future.

PC

No responses yet