Archive for December, 2010

Dec 14 2010

TCAD present state and future challenges – IEDM 2010

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At the recent IEDM conference in San Francisco, Synopsys presented an invited paper on where Technology CAD is today and the challenges for supporting future processes.  There was a short history of standard TCAD from 1D modeling to the present need for 3D models.    The conventional TCAD is based on solving device physics equations with numerical processing of Partial Differential Equations (PDE) and simultaneous equations in matrices.  These euqations are for Poisson’s eq, diffusion, heat, hydro-dynamics, density, implants and dosing, and oxidation.  This has been the baseline TCAD since the 1980′s where the models were 1D, had about 100 points in the mesh, and solved for about 200 unknowns.  In the 2010, the process complexity requires 3D models, about 1M points in the mesh, and about 10M unknowns to solved for.
An issue for TCAD has been the “reach” of the simulation also known as the “size of the sample” area.  While in the 80′s this started with a window and mesh size that did not even cover the extent of most devices, today the widow size, while still in the low microns range, now covers multiple devices.  This has driven TCAD to have to perform application specific use modeling for CMOS, memories, analog, power devices, image sensor devices, solar devices, and TSVs.  TCAD is still a mainstay of advanced process development.  A typical process development is ~$1.1B for 45nm, ~$1.6B for 32nm, and >$2B for 22nm.  The ITRS roadmap and recommended flows indicate that modeling with TCAD can reduce the costs of the development cycles by ~30%.
Advancements in current TCAD simulation can help with complex what if scenarios such as bulk vs SOI use on device stress and Hi-K metal gate with SiGe strain enhancement tradeoffs.  The resulting process variability can now be simulated for RDF (random doping fluctuations) and LER (line edge roughness) in addition to the normal targeted solutions.
The challenges come modeling the devices below 20nm.  The reality is that a 90nm process has an Leff of ~25nm, and a 32nm process also has an Leff of ~24nm, so there is very little change in the Leff scaling.  Below 20nm this stays about the same, as the channel itself does not scale.  At these geometries, the effects that additionally have to be modeled include: strain, BTBT, Chanel mobility, quasi-ballistic transport and s/d tunneling (quantum transport).  In order to solve these equations, the simulations an still take several days.
New materials are bringing new challenges, graphene and nano-wires behave under different operating equations than CMOS or traditional III-V devices.  For these devices, atomistic modeling using kinetic Monte Carlo (kMC) methods have to be employed.  In order to address the scaling toward the end of the ITRS roadmap, new material property analysis is needed and due to the scale, ab-initio computation methods on these materials have to be employed.  This means they have to start at the particle and molecule level, then move to groups and concentrations of the particles until the multi-material interactions can be simulated.
The field of TCAD is being both guided and limited by the state of development and understanding of the material characterization of elements such as spintronic materials, graphene, nano-wire materials, and other carbon based transistors.  The field of TCAD is working on computational methods to decase the effective clock time that is elapsed during the simulations.
PC

At the recent IEDM conference in San Francisco, Synopsys presented an invited paper on where Technology CAD is today and the challenges for supporting future processes.  There was a short history of standard TCAD from 1D modeling to the present need for 3D models.    The conventional TCAD is based on solving device physics equations with numerical processing of Partial Differential Equations (PDE) and simultaneous equations in matrices.  These euqations are for Poisson’s eq, diffusion, heat, hydro-dynamics, density, implants and dosing, and oxidation.  This has been the baseline TCAD since the 1980′s where the models were 1D, had about 100 points in the mesh, and solved for about 200 unknowns.  In the 2010, the process complexity requires 3D models, about 1M points in the mesh, and about 10M unknowns to solved for.

An issue for TCAD has been the “reach” of the simulation also known as the “size of the sample” area.  While in the 80′s this started with a window and mesh size that did not even cover the extent of most devices, today the widow size, while still in the low microns range, now covers multiple devices.  This has driven TCAD to have to perform application specific use modeling for CMOS, memories, analog, power devices, image sensor devices, solar devices, and TSVs.  TCAD is still a mainstay of advanced process development.  A typical process development is ~$1.1B for 45nm, ~$1.6B for 32nm, and >$2B for 22nm.  The ITRS roadmap and recommended flows indicate that modeling with TCAD can reduce the costs of the development cycles by ~30%.

Advancements in current TCAD simulation can help with complex what if scenarios such as bulk vs SOI use on device stress and Hi-K metal gate with SiGe strain enhancement tradeoffs.  The resulting process variability can now be simulated for RDF (random doping fluctuations) and LER (line edge roughness) in addition to the normal targeted solutions.

The challenges come modeling the devices below 20nm.  The reality is that a 90nm process has an Leff of ~25nm, and a 32nm process also has an Leff of ~24nm, so there is very little change in the Leff scaling.  Below 20nm this stays about the same, as the channel itself does not scale.  At these geometries, the effects that additionally have to be modeled include: strain, BTBT, Chanel mobility, quasi-ballistic transport and s/d tunneling (quantum transport).  In order to solve these equations, the simulations an still take several days.

New materials are bringing new challenges, graphene and nano-wires behave under different operating equations than CMOS or traditional III-V devices.  For these devices, atomistic modeling using kinetic Monte Carlo (kMC) methods have to be employed.  In order to address the scaling toward the end of the ITRS roadmap, new material property analysis is needed and due to the scale, ab-initio computation methods on these materials have to be employed.  This means they have to start at the particle and molecule level, then move to groups and concentrations of the particles until the multi-material interactions can be simulated.

The field of TCAD is being both guided and limited by the state of development and understanding of the material characterization of elements such as spintronic materials, graphene, nano-wire materials, and other carbon based transistors.  The field of TCAD is working on computational methods to decase the effective clock time that is elapsed during the simulations.

PC

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