Archive for November, 2010

Nov 18 2010

Devices and Litho for sub 17nm process

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On Tues Nov 16, the IEEE Nanotech Council held a 1/2 day event on the challenges and innovation for the world of sub 20nm device processing.  Speaking were Applied Materials, TSMC, Global Foundries and Tablula.  The overall theme was that, while there are challenges, both business and technical, there are solution paths that are being sought and providing results.  The litho, fabrication and design architecture will be shifting from today to address the needs of the process, but there will be solutions available on the current schedule proposed by ITRS.

Chris Bencher from AMAT presented how there are muliple techniques to get to 15nm resolution for litho – some are available now, and some soon.  The current method is with quad-patterning techniques.  The hope for upcoming technology is the use of EUV with double patterning.  The current solution has some challenges from line edge roughness and resist material, that are addressed and improved with EUV-DP.  Di Ma from TSMC mentioned in the panel discussion, the real challenge is thoughtput for these solutions.  For production applications, these techniques need to support 60-100 wafers/per hour, and currently the techniques are not there yet.
TSMC and GlobalFoundries had a desicription of their HKMG flows that feature “gate last” for TSMC, and “gate first” for Global.  TSMC went with gate last based on optimization of 5 simultaneous desgin/device characteristics of the devices, and Global focused on optimization of 2 key aspects.   In the panel discussion, Nick Kepler of Global mentioned that he was not sure what all the fuss is about – in the past there were 30-50 fabs who all had different process flows and manufacturing techniques, now that there a only a few fabs, why the big deal if they have different flows?
Di and Nick also discussed directions in 3D ICs, stacked die and TSVs.  These technologies are progressing rapidly and are aimed at the massive interconnect problem for new designs.  The delay times through I/O is very long and the pin counts of CPU/GPU/Memory based systems are in the 5000+ range, which is impractical for traditional edge based I/O with wrie bonds.
Steve Teig of Tablua discussed that the interconnect problem was not just limited to die to die communication, but was also the major limiter in current ICs and FPGAs.  Steve discussed some of the challenges, even at advanced process nodes, of FPGAs addressing the price performance metrics currently achived by ASICs.  He reviewed some the architectural changes for FPGAs that are needed, the new architecture of the Tabula product,  as well as throwing down the gauntlet at the programming environments .  He expressed the opinion that trying to describe chips and logic design with the C programming language is not the best fit as the structure of the C-Language is not directly compatible or optimized for the way hardware is built.
The event featured a panel discusion with the four speakers moderated by M&E Tech’s EIC Tets Maniwa who lead an interactive Q&A on the timelines of some of these litho and device tradeoffs as well as expanding on the collaboration cycle for new development.
PC

Chris Bencher from AMAT presented how there are muliple techniques to get to 15nm resolution for litho – some are available now, and some soon.  The current method is with quad-patterning techniques.  The hope for upcoming technology is the use of EUV with double patterning.  The current solution has some challenges from line edge roughness and resist material, that are addressed and improved with EUV-DP.  Di Ma from TSMC mentioned in the panel discussion, the real challenge is thoughtput for these solutions.  For production applications, these techniques need to support 60-100 wafers/per hour, and currently the techniques are not there yet.

TSMC and GlobalFoundries had a desicription of their HKMG flows that feature “gate last” for TSMC, and “gate first” for Global.  TSMC went with gate last based on optimization of 5 simultaneous desgin/device characteristics of the devices, and Global focused on optimization of 2 key aspects.   In the panel discussion, Nick Kepler of Global mentioned that he was not sure what all the fuss is about – in the past there were 30-50 fabs who all had different process flows and manufacturing techniques, now that there a only a few fabs, why the big deal if they have different flows?

Di and Nick also discussed directions in 3D ICs, stacked die and TSVs.  These technologies are progressing rapidly and are aimed at the massive interconnect problem for new designs.  The delay times through I/O is very long and the pin counts of CPU/GPU/Memory based systems are in the 5000+ range, which is impractical for traditional edge based I/O with wrie bonds.

Steve Teig of Tablua discussed that the interconnect problem was not just limited to die to die communication, but was also the major limiter in current ICs and FPGAs.  Steve discussed some of the challenges, even at advanced process nodes, of FPGAs addressing the price performance metrics currently achived by ASICs.  He reviewed some the architectural changes for FPGAs that are needed, the new architecture of the Tabula product,  as well as throwing down the gauntlet at the programming environments .  He expressed the opinion that trying to describe chips and logic design with the C programming language is not the best fit as the structure of the C-Language is not directly compatible or optimized for the way hardware is built.

The event featured a panel discusion with the four speakers moderated by M&E Tech’s EIC Tets Maniwa who lead an interactive Q&A on the timelines of some of these litho and device tradeoffs as well as expanding on the collaboration cycle for new development.

PC

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