Archive for June, 2010

Jun 09 2010

Silicon Frontline – Field Solvers Finally Make the Reference Flow

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Silicon Frontline has been seeing success with thier field solver based IC tools for RC extraction and Resistance extraction for power circuits.  The tools have been adopted by multiple commercial customers who have used the tool fo over 200 design releases.  These design releases ranged from IP blocks on Multi-Project Wafers (MPWs) and full stand-alone designs.
The performance capabilities of the Resisttance extractor tothe point that it is used to create the reference extraction data for new UMC processes.  The tool is also the preferred tool for both standalone use and reference flow work ,    TSMC has also approved the products – both xRC and distributed R for the 32/28nm node.  This means the IP development flow that is used is the same flow that is featured for full SOC designs.
There are addition fabs that will be announced in 2010, as the qualification cycle and identification of flows for sub 40nm processes takes place.  The tool is in qualification on several other process nodes at this time.
An area of expansion for the product is the I/O cells and 3D assembly including TSVs.  These strucutures have been an area of great difficulty to accurately model, but they are very well adapated to full 3D field solvers.  One of the field solver constraints in the past has been a short reach/long reach problem in a common environment.  With breakthroughs in multicore SDKs , the code can accommodate the small geometries of the process and the large dimensions of the TSVs.  This feature is targeted for a future release.
PC

Silicon Frontline has been seeing success with thier field solver based IC tools for RC extraction and Resistance extraction for power circuits.  The tools have been adopted by multiple commercial customers who have used the tool fo over 200 design releases.  These design releases ranged from IP blocks on Multi-Project Wafers (MPWs) and full stand-alone designs.

The performance capabilities of the Resisttance extractor tothe point that it is used to create the reference extraction data for new UMC processes.  The tool is also the preferred tool for both standalone use and reference flow work ,    TSMC has also approved the products – both xRC and distributed R for the 32/28nm node.  This means the IP development flow that is used is the same flow that is featured for full SOC designs.

There are addition fabs that will be announced in 2010, as the qualification cycle and identification of flows for sub 40nm processes takes place.  The tool is in qualification on several other process nodes at this time.

An area of expansion for the product is the I/O cells and 3D assembly including TSVs.  These strucutures have been an area of great difficulty to accurately model, but they are very well adapated to full 3D field solvers.  One of the field solver constraints in the past has been a short reach/long reach problem in a common environment.  With breakthroughs in multicore SDKs , the code can accommodate the small geometries of the process and the large dimensions of the TSVs.  This feature is targeted for a future release.

PC

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