Archive for April, 2010

Apr 19 2010

ASQED Final Call For Papers

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The ISQED- Asia conference on Quality Electronic Design, is being held in Penang,  Malaysia on August 3-4, 2010.  The final call for papers for the event is through this Friday 4/23/10, and is seeing papers on manufacturing, design and tools.  Information on how to submit a paper is at :  http://www.asqed.com/ .

There are over sixty (60) papers on the topics of -
O  Circuit & System Design
O  Test & Verification
O  IC Packaging Technology
O  PCB and PWB Technology & Manufacturing
O  Semiconductor & Nano Technology
O  Bio Electronics Innovations
O  Photovoltaic Technology & Manufacturing
O  Electronic Design Automation Methodologies
O  Micro-Electro-Mechanical System (MEMS)

scheduled for the event.

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Apr 18 2010

U2U 2010- Calibre and AMS focus on design

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The Calibre and AMS groups at the Mentor U2U event in Santa Clara had customer presentations that were very design solution oriented rather than CAD oriented.  Unlike some of the User Group events from other suppliers, the focus was on innovative customer solutions using the tools, NOT tool configuration and benchmarks.

The Calibre sessions has a number of presentation on the new PERC product.  Cypress Semi presented how they were able to use the new tool to not only capture and quantify their ESD rules, but also apply them in multiple situations.  Traditionally, ESD has been a peripheral I/O components.  With multiple power supplies and dynamic power switching in a design, there are some internal ESD rules dealing with these voltage levels adjacencies and transient on-off states for devices.  They were able to show how the tools automated these checks and some of the equations and mechanisms involved for the issues.  The customer did not as yet implement auto-fix of these errors, but that is on the road map.

On the AMS side, ST presented a PLL simulation.  Focusing on the structured use of the .IC statement to save state in a design, they showed how they were able to simulate a PLL using their AMS and device level RF tools.    The key detail was being able to setup the simulation so the non-harmonic divisor mode(divv by 5), did not impact the simulation results for the harmonic sub frequencies (div by 8).  Since the normal solution is to do a long simulation with a divide by 40 clock (or a 1/40th clock), the ST solution showed a multiple IC session methodology that reduced the simulation time by directly supporting the divide by 8 mode and tracking the device and model variations.  They also showed how the tools could automate the function of saving and reloading the .IC conditions.

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