Mar 08 2010
ISSCC 2010 – Low power designs back on track By Anand Iyer
Importance of low power has never been more pronounced as with this year’s ISSCC. Low power designs were highlighted in number of sessions throughout the conference. Some of the memorable ones were from Intel on the application of DVFS technique to 80-core processor, the clock power reduction using pulse latches in Power 7 by IBM and low power techniques applied to the AMD 32nm processor (Bulldozer?).
These processors highlight significant improvements in the application of low power techniques on real designs. Such real world design practices should encourage more interest in this area and enable some of the difficult techniques to be realized in silicon.
Low power techniques are always built on simple principles. For example, making prudent choices for architecture like limiting the bandwidth, not redoing tasks that are completed, and working only when needed are simple principles which should reduce the overall power consumption. Yet, implementation is quite complex because of the integration demanded in the modern processors and other design-imposed limitations. As we know that with every subsequent process migration, transistors are becoming cheaper. Designers would make use of these transistors by either performing more computations (multi-core) or integrating more functions. If the designers are not careful with defining the architectures, power inefficiencies can exists.
The first paper from Intel (session 9.01) studied the effect of DVFS technique on 80-core 65nm NOC processor. The processor was devised such that each of the 80-cores can be voltage and frequency controlled all the way to shutting down completely. The measurement was conducted with varying loads of traffic. Intel used proprietary scheduling techniques to come up with voltage and frequency numbers for each processors based on the load. The results were fairly intuitive that voltage variation had a bigger effect on power than the frequency variation (voltage is the square term in the power equation).
The second paper (session 9.03) highlighted some of the interesting low power concepts applied to the Power7 architecture. Power 7 designed in 45nm SOI process uses pulse clocking in order to save power. They use full master-slave configuration, but keep the master stage ON at all times during the pulsed mode operation. Data flows through the master stage and only slave stage is used for storage. For testing purposes, the master stage functionality is restored. IBM reported about 20% power savings by employing this technique.
AMD’s processor (session 5.06), designed in 32nm SOI process had several new low power techniques implemented. AMD presented two power saving techniques and one for on-chip power measurement. The first method was to control clock power which contributes ~30% of power. To control clock power, AMD did a careful clock gater placement and implemented fine grain and multi-stage clock gating. Secondly, it used power gating throughout to control the power with shutting down the processor. AMD got away using footer devices because of the SOI process. And finally AMD designed a circuit to monitor power by monitoring a few of the critical signals for activity.
Overall, there has been rich low power design content in this year’s ISSCC. Readers can check out the proceedings for other interesting papers. After a forgettable 2009, this year has started a lot better and seems like the low power designs are back on track. This has increased our hopes of seeing more and more low power designs in future conferences.
AI