Mar 05 2010

Big die, multi-die, thin die and patents

Published by at 11:56 am under Uncategorized

At the MEPTEC Chip to System symposium there a lot of discussion about the silicon that fits in the packages in addition to the package.  The opening keynote from Tom Gregorich framed the conference with the premise that chip scaling is going to be limited by the reality that sometimes users need to put the analog/MEMS and the digital/memory functions together in a single package and they can’t be built on the same chip due to technology differences and cost.  These are a combination of design, fab, test and assembly costs.
One of the drivers in the packaging arena is package size and pin pitch.  The form factor for many devices are driving the investigation of tight package pitches down to 0.3mm per pin, however these have a drawback of expensive PCBs and board level assembly, as well as thermal dissipation issues.  On the scaling side, Cisco presented another design tradeoff issue for networking Ics.  For higher data rates and throughput, they are pushing the process envelope to smaller geometries, and more parallel data processing (more channels per chip).  This is creating a pin count explosion and a heat dissipation per unit area issue with the die.  Cisco indicated that they are currently building 20mm/side die, and would like to go larger to address getting all the pins on and spreading the heat out, but they are running in to the litho field size and yield with these large die.  One of the areas to help with these issues is the development of low loss power delivery methods between PCB and die with the associated increase in thermal density handling.
Additional speakers discussed the 3D assembly techniques focusing on handling challenges for very thin (20um thickness) 300mm wafers that have been mechanically backlapped for TSV assembly.  These issues include die separation, particle defect creation and post-thin testing.  The discussion was then carried forward to the topic of BIST, scan development and post assembly testing for systems with TSVs and accessability issues to embedded and burried functions in the internal die stacks of the TSV modules.  The forecast for TSV in production is 2012 for DRAM for server applications, 2013 for use in FPGA/Memory systems, and 2014 for microprocessor/ memory applications,  From a die stacking approach, non-TSV die stacking wafers presented as a current high volume technology with over 2.5B stacked memory modules have been shipped with 2 to 8 die.  The technology has been shown to support up to 17 die stacks in R&D.
The conference ended with an open panel discussion (the panel session was open to the public, not just registered attendees) on patent and IP issues.  The lively discussion included protection in the US and Japan vs India/China policies and realities, patent trolls, and the new vehicle – the patent agitator.  This vehicle is typically a law firm or licencing organization that buys or becomes a licensee of key technology patents in bulk, and then re-licenses the entire portfolio in “insurance” mode to companies that may end up with infringement issues and are not in a position to individually negotiate and license hundreds to thousands of patents for a given project.
PC

At the MEPTEC Chip to System symposium there a lot of discussion about the silicon that fits in the packages in addition to the package.  The opening keynote from Tom Gregorich framed the conference with the premise that chip scaling is going to be limited by the reality that sometimes users need to put the analog/MEMS and the digital/memory functions together in a single package and they can’t be built on the same chip due to technology differences and cost.  These are a combination of design, fab, test and assembly costs.

One of the drivers in the packaging arena is package size and pin pitch.  The form factor for many devices are driving the investigation of tight package pitches down to 0.3mm per pin, however these have a drawback of expensive PCBs and board level assembly, as well as thermal dissipation issues.  On the scaling side, Cisco presented another design tradeoff issue for networking Ics.  For higher data rates and throughput, they are pushing the process envelope to smaller geometries, and more parallel data processing (more channels per chip).  This is creating a pin count explosion and a heat dissipation per unit area issue with the die.  Cisco indicated that they are currently building 20mm/side die, and would like to go larger to address getting all the pins on and spreading the heat out, but they are running in to the litho field size and yield with these large die.  One of the areas to help with these issues is the development of low loss power delivery methods between PCB and die with the associated increase in thermal density handling.

Additional speakers discussed the 3D assembly techniques focusing on handling challenges for very thin (20um thickness) 300mm wafers that have been mechanically backlapped for TSV assembly.  These issues include die separation, particle defect creation and post-thin testing.  The discussion was then carried forward to the topic of BIST, scan development and post assembly testing for systems with TSVs and accessability issues to embedded and burried functions in the internal die stacks of the TSV modules.  The forecast for TSV in production is 2012 for DRAM for server applications, 2013 for use in FPGA/Memory systems, and 2014 for microprocessor/ memory applications,  From a die stacking approach, non-TSV die stacking wafers presented as a current high volume technology with over 2.5B stacked memory modules have been shipped with 2 to 8 die.  The technology has been shown to support up to 17 die stacks in R&D.

The conference ended with an open panel discussion (the panel session was open to the public, not just registered attendees) on patent and IP issues.  The lively discussion included protection in the US and Japan vs India/China policies and realities, patent trolls, and the new vehicle – the patent agitator.  This vehicle is typically a law firm or licencing organization that buys or becomes a licensee of key technology patents in bulk, and then re-licenses the entire portfolio in “insurance” mode to companies that may end up with infringement issues and are not in a position to individually negotiate and license hundreds to thousands of patents for a given project.

PC

No responses yet

Trackback URI | Comments RSS

Leave a Reply